SRC: instruction formats
Op-code
ra
rb
rc
c3
0
11
12
16
17
21
22
26
27
31
Type D
Op-code
0
26
27
31
Type A
unused
Op-code
ra
0
22
26
27
31
Type B
c1
21
Op-code
ra
rb
0
16
17
21
22
26
27
31
Type C
c2
CS501Advanced ComputerArchitecture
Lecture04
Dr.Noor Muhammad Sheikh
Encoding for the GPRsto be used in place of ra, rb, or rc
RegisterRegister
CodeCode
RegisterRegister
CodeCode
RegisterRegister
CodeCode
RegisterRegister
CodeCode
R0
00000
R8
01000
R16
10000
R24
11000
R1
00001
R9
01001
R17
10001
R25
11001
R2
00010
R10
01010
R18
10010
R26
11010
R3
00011
R11
01011
R19
10011
R27
11011
R4
00100
R12
01100
R20
10100
R28
11100
R5
00101
R13
01101
R21
10101
R29
11101
R6
00110
R14
01110
R22
10110
R30
11110
R7
00111
R15
01111
R23
10111
R31
11111
Notes: simple 5-bit encoding as shown above; ra, rb, rc are names of fields,used as “place-holders”, and can represent any one of these 32 registers.
Except: rb =0 does not mean R0; explained later
Type A
Op-code
0
26
27
31
unused
Only two instructions
nop (op-code = 0)
•useful in pipelining
stop (op-code = 31)
Both are 0-operand
three instructions; all three use relative addressing mode
ldr (op-code = 2 ) load register from memory using relative address
ldr R3, 56R[3] M[PC+56]
lar (op-code = 6 ) load register with relative address
lar R3, 56R[3] PC+56
str (op-code = 4) store register to memory using relative address
str R8, 34M[PC+34] R[8]
the effective address is computed at run-time by adding aconstant to the PC
makes the instructions relocatable
Type B
Op-code
ra
0
22
26
27
31
c1
21
Note: R8 is register name and R[8] means contents of register R8
Type C
Op-code
ra
rb
0
16
17
21
22
26
27
31
c2
three load/store instructions, plus three ALU instructions
ld (op-code = 1 ) load register from memory
ld R3, 56 R[3] M[56] (rb field = 0)
ld R3, 56(R5)R[3] M[56+R[5]] (rb field ≠ 0)
la (op-code = 5 ) load register with displacement address
la R3, 56R[3] 56
la R3, 56(R5)R[3] 56+R[5]
st (op-code = 3 ) store register to memory
st R8, 34M[34]R[8]
st R8, 34(R6)M[34+R[6]] R[8]
direct addressingmode
Indexedaddressingmode
Immediate addressing mode
Indexedaddressingmode
direct addressingmode
Type C(continued…)
Op-code
ra
rb
0
16
17
21
22
26
27
31
c2
….and the three ALU instructions
addi (op-code = 13)immediate 2’s complement addition
addi R3, R4, 56 R[3] R[4]+56 (rb field = R4)
andi (op-code = 21) immediate logical AND
andi R3, R4, 56R[3] R[4]&56
ori (op-code = 23)immediate logical OR
ori R3, R4, 56R[3] R[4]~56
Note special symbolused for AND
If the constantis negative,this becomesa subtractinstruction
register addressing mode
Type C(modified form)
Op-code
ra
rb
0
16
17
21
22
26
27
31
unused
….(additional) four shift instructions
shr (op-code = 26)shift right by using value in (5-bit) c3 field
shr R3, R4, 7 shift R4 right 7 times in to R3
shra (op-code = 27) Arithmetic shift right by using value in c3 field
shra R3, R4, 7Ashift R4 right 7 times in to R3
shl (op-code = 28)shift left by using value in (5-bit) c3 field
shl R8, R5, 6shift R5 left 6 times in to R8
shc (op-code = 29)shift left? circular by using value in c3 field
shc R3, R4, 3shift R4 circular 3 times in to R3
Note: If count field contains 0, then these instructions will use the modified Type D format
4
count
All use immediate addressing mode
Type D
four ALU instructions, plus others explained on following slides
add (op-code = 12) 2’s C register addition
add R3, R5, R6 R[3] R[5] + R[6]
sub (op-code = 14) 2’s C register subtraction
sub R3, R5, R6R[3] R[5] - R[6]
and (op-code = 20) logical AND operation between registers
and R8, R3, R4R[8] R[3] & R[4]
or (op-code = 22) logical OR operation between registers
or R8, R3, R4R[8] R[3] ~ R[4]
register addressing mode
Op-code
ra
rb
rc
unused
0
11
12
16
17
21
22
26
27
31
Type D(modified form)
… four register based shift instructions, plus…
shr (op-code = 26)shift right by using value in register rc
shr R3, R4, R5 shift R4 right in to R3 using number in R5
shra (op-code = 27) Arithmetic shift right by using register rc
shra R3, R4, R5Shift R4 right as above
shl (op-code = 28)shift left by using register rc
shl R8, R5, R6shift R5 left in to R8 using number in R6
shc (op-code = 29)shift circular by using register rc
shc R3, R4, R6shift R4 circular in to R3 using value in R6
Op-code
ra
rb
rc
unused
0
11
12
16
17
21
22
26
27
31
5
4
00000
All use the register addressing mode
Type D(modified formsfor branch instr )
… plus two branch instructions
br (op-code = 8)branch to address in rb depending oncondition in rc (five possible conditions)
brzr R3, R4 branch to address in R3 (if R4 == 0)
brnz R3, R4 branch to address in R3 (if R4 ≠ 0)
brpl R3, R4 branch to address in R3 (if R4 ≥ 0)
brmi R3, R4 branch to address in R3 (if R4 < 0)
br R3 branch to address in R3 (unconditional)
Op-code
unused
rb
rc
unused
0
11
12
16
17
21
22
26
27
31
3
2
cond
Type D(modified formsfor branch instr )
brl (op-code = 9) branch to address in rb depending on condition inrc. Additionally, copy the PC in to ra before branching
Op-code
ra
rb
rc
unused
0
11
12
16
17
21
22
26
27
31
3
2
cond
Branch and linkexamplesBranch and linkexamples
FunctionFunction
brlzr R1,R3, R4
R[1] PC, then branch to address in R3 (if R4 == 0)
brlnz R1,R3, R4
R[1] PC, then branch to address in R3 (if R4 ≠ 0)
brlpl R1,R3, R4
R[1] PC, then branch to address in R3 (if R4≥ 0)
brlmi R1,R3, R4
R[1] PC, then branch to address in R3 (if R4 < 0)
brl R1,R3
R[1] PC, then ALWAYS branch to address in R3
brlnv R1
R[1] PC, NEVER BRANCH
ConditionCodes
Op-code
unused
rb
rc
unused
0
11
12
16
17
21
22
26
27
31
5
2
cond
MnemonicMnemonic
c3<2..0>c3<2..0>
Branch ConditionBranch Condition
brlnv
000
Link but never branch*
br, brl
001
Unconditional branch
brzr, brlzr
010
Branch if rc is zero
brnz, brlnz
011
Branch if rc is not zero
brpl, brlpl
100
Branch if rc is positive
brmi, brlmi
101
Branch if rc is negative
* “Branch never” i.e., brnv, does not exist
9
3
0
1
minus
Table 2.6, page 58, text