Lattice Semiconductor Corporation

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JTAG

February 2001 1

Lattice Confidential

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Lattice SemiconductorThe Leader in ISPTM PLDsPresents

A Guide to JTAG Programming andTestA Guide to JTAG Programming andTest

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JTAG

February 2001 2

Lattice Confidential

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Bscan Overview

•Since 19970’s Testing of populated PCB’s has relied on Bed of Nail’stesters.

•A new concept has now evolved which uses the pins of the IC’s on the PCB.

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JTAG

February 2001 3

Lattice Confidential

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Bscan Overview

•Bed-of-nails testing involves accessing individual devices on theboard through test lands laid into the copper interconnect, or otherconvenient contact points.

•Testing of PCB’s using a Bed-of-nails can take the following form :-

•Power-off tests and Power-on tests.

•Power-off tests check the integrity of the physical contact betweennail and the on-board access point. Followed by open and shortstests based on impedance measurements.

•Power-on tests apply stimulus to a specific device on a board,which is accompanied by a measurement of the response from thedevice.

•Devices which are not being tested are put into a safe state (Alloutputs Tri-Stated or isolated) in order to avoid signal contention.

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JTAG

February 2001 4

Lattice Confidential

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Bscan Overview

•Bed-of-nails testing has several major draw backs:-

•Physical space requirements on the PCB for the nail contacts.

•Limit on the number of feasible connection points on the PCB.

•Inability to test new surface mount packages ie: BGA as contactpoints for the all the required bed-of-nails points becameimpossible.

•Each new PCB requires a new test fixture, which can involve asignificant cost.

•The ATE’s that perform the testing require significant capitalexpenditure.

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JTAG

February 2001 5

Lattice Confidential

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Bscan Overview

•In the mid-1980s a group of concerned European test engineerssought a solution to the issues of PCB testing using the bed-of-nails technique.

•The participants formed an organisation called Joint European TestAction Group (JETAG).

•This organisations goal was to find a solution to PCB testing due tothe draw backs from the existing bed-of-nails method.

•The concept of a serial shift register around the boundary of theeach individual device became the preferred solution.

•This is where term “Boundary Scan” originated from.

•After a period of time American companies joined the JETAGorganisation, at this point in time the ‘E’ was dropped and itbecame the Joint Test Action Group (JTAG).

•JTAG is the organisation responsible for creating the internationalstandard.

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JTAG

February 2001 6

Lattice Confidential

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Bscan Overview

•The “boundary Scan” or otherwiseknown as the TAP (Test AccessPort) controller requires 4dedicated pins and 1 optional.

•The dedicated pins are : TDI (TestData In),TDO (Test Data Out),TMS(Test Mode Select),TCK (TestClock)

•The optional pins is TRST (TestReset)

• The “Boundary Scan” cells areconnected on every primary inputand output of a device to form aserial chain round the device.

$C:\peter\goepl\circuit.gif$

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JTAG

February 2001 7

Lattice Confidential

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Bscan Overview

•The TAP controller consists of a finite state machine with 16 uniquestates.

•The State transitions are primarily controlled by TMS and TCLK(TRST will also return the state machine to Test-Logic-Reset. Thisoperation can also be performed if TMS is held at a ‘1’ for 5 or moreclock cycles).

•The Instruction Register in the device must be at least 2 bits wide.

•There must also be implemented a Bypass register which willfacilitate the bypass of the “Boundary Scan“ cells.

•Also to enable the identification of different manufactures devicesin a chain. The support of a 32 bit ID register which holds uniquecodes can be implemented.

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JTAG

February 2001 8

Lattice Confidential

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Bscan Overview The TAP State Diagram

$C:\peter\statetab.gif$

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JTAG

February 2001 9

Lattice Confidential

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Bscan Overview The Instruction Register

$C:\peter\dev_id.gif$

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JTAG

February 2001 10

Lattice Confidential

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Bscan Overview

•Only one of the possible internal registers can be connected fromthe TDI to TDO path.

•The connection between TDI and TDO is controlled by the decodingof the instruction in the IR Register.

•The JTAG specification provides for mandatory instructions ie:-Extest, Bypass, Sample/Preload which must be supported by allsilicon vendors.

•The JTAG specification also provides for optional instructions ie :-IDCODE.

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JTAG

February 2001 11

Lattice Confidential

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Bscan Overview Application on a PCB

•The initial tests after power on would be to normally capture and shift theinstruction register contents. The Patterns chosen will ensure that theintegrity of the “Boundary Scan” chain.

•Next if supported by the device it would be possible to test the internal logicof the device using the Intest or RunBist instructions.

$C:\peter\intest.gif$

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JTAG

February 2001 12

Lattice Confidential

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Bscan Overview Application on a PCB

•The PCB is at a state where the devices in the “Boundary Scan” chain orknow to be operational. The user will wish to perform checks on the PCBand the manfacturing flow. This is performed by the use of the ExtestInstruction.

•Extest enables the pins on the device to act as either inputs or outputs tothe PCB.

$C:\peter\extest.gif$