Instruction Set Architecture
The portion of the machine visible to theprogrammer
Issues:
Internal storage model
Addressing modes
Operations
Operands
Encoding
Compilation Issues
Internal Storage Model
Memory- Memory (Add C, A, B)
Internal Storage Model
Most post 1980 architectures use a load storearchitecture
Main reasons
registers faster than memory
Compilers can utilise registers more effectivelythan other models
Variables can be held in registers
Instruction set can use 2 or 3 operand format
Memory Addressing
How
memory addresses interpreted
memory addresses are specified
Interpretation
Size (byte, half word, word)
Ordering (Big Endian, Little Endian)
Alignment (Word)
Memory Addressing(Addressing modes)
How an address is specified
Modes included on machines:
Register (e.g. Add R4, R3)
Immediate (e.g. Add R4, #3)
Displacement (e.g. Add R4, 100(R1))
Absolute (Add R4, (1000))
Memory Indirect (Add R4 @(R3))
Autoincrement (Add R4, (R1)+)
Autodecrement (Add R4, -(R1))
Memory Addressing
Use of addressing Modes:
register accounts for 50% (not counted below)
1%
Displacement
What is the range of displacementsused
Immmediate
Immediate
Operations in the InstructionSet
Can be classified into the followingtypes
Arithmetic and logical
Data transfer
Control
System
Top 10 instructions on 8086
Averaged over 5 SPECin92 programs
Instructions for Control Flow
Four types
Conditional Branches
Jumps
Procedure Calls
Procedure returns
Destination address must always be supplied.Can be:
specified explicitly
indirect jumps (procedure return)
Branch Distance
PC relative Branching
Target often close to the branchinstruction
Destination is obtained by adding adisplacement to the PC
Requires fewer bits to encodeinstruction
helps make code position independent
Specifying Branch Condition
Most branches are equality|inequality testsor comparisons with zero
Type and Size of Operands
Two main alternatives
operand types specified in opcode(e.g. add, addb, addf)
data annotated with tags(very rare)
Encoding the Instruction Set
Representation affects
size of compiled program
implementation of CPU
Architect must balance
the desire to have as many registers andaddressing modes as possible
the impact of the size of register andaddressing mode fields
VIARABLE (e.g. VAX, 68000)
Better code density
FIXED (e.g. MIPS and PowerPC)
Simpler hardware
Variations in Instructiondecoding
Opcode
Result
Operand 1
Operand 2
Opcode
Add spec 1
Add field 1
Add spec n
Add field n
...
Example 1: A Registerlessprocessor
L1 Cache and registers about samespeed
no need for registers
An fixed length instruction set with 3operand format is proposed
Simulations show that the number ofinstructions execution is about half of aload store architecture