ECE 506Reconfigurable Computinghttp://www.ece.arizona.edu/~ece506Lecture 5Logic Block ArchitectureAli Akoglu
FPGA Design, Symmetrical Architecture Approach
Architectural Issues – Ahmed and Rose
•What values of N, I, and Kminimize the followingparameters?
-Area
-Delay
-Area-delay product
Architectural Issues – Ahmed and Rose
°What is a high stress routing?
°What are the potential problems with measuring criticalpath delay under high stress routing?
°How are these issues avoided?
•Routing using minimum number of tracks neededfor the circuit
•This leads to increased routing execution time
•Inconsistent results in delay
•Solution: relax CW by 30%
Design Flow
Background Check
°What is the role of a buffer?
•isolate other gates or circuits from each other
•drive high current loads
•high "fan-out" capability
-for power amplification of a digital signal
•output of a logic gate usually connected to the inputs of othergates.
•each input requires a certain amount of current from the gateoutput to change state,
•each additional gate connection adds to the load of the gate.
Architectural Issues – Ahmed and Rose
Fcin fixed!
# of muxes tofeed intoincreases with N
Fully Connected Clusters
•Require fewer than full KxN inputs to achieve high logic utilization:
-input sharing,
-output-input sharing,
-some LUTs not requiring all inputs to be used,
-I=K/2*(N+1) (50%-60% is good enough for 98%, hence /2)
•Reducing inputs reduces the size of the device and makes it faster.
Before Placement: Clustering
°Academic studies typicallyconsider fully populated(connected) logic cluster:
•Simpler to write CAD tools
Before Placement: Clustering
°Commercial parts:depopulated
°(this is 50%)
Effect of N and K on Area
°Reduction in total area as cluster size is increasedfrom 1 to 3 for all LUT sizes.
°As clusters are made larger (N>4), there is little impacton total FPGA area.
Effect of N and K on Area
°intercluster area
•more external connections localized, reducing area
•number of inputs/outputs increase per CLB, this increases the trackcount leading to increase in intercluster area
°intracluster area
•more MUXes are used in the CLB, increasing area
As N increases
Intracluster area with respect to K
faster pace in increasein logic area thandecrease in number ofCLBs.
Intercluster area with respect to K
As K increases, number of clusters decreasesfaster than the rate of increase in external routingarea.
Delay vs K and N
rate of change in BLE, CLB and inter-cluster delays,
rate of change in the number of BLEs and CLBs on critical path
Effect of N and K on Area-delay product
K = 4-6, N= 4-10 looks OK
