PowerPoint Presentation

SRS Trigger Processor OptionStatus and Plans

Sorin Martoiu (IFIN-HH)

ATCA-SRS Status

•First systems delivered

–IFIN-HH

–UPV and

–CERN (MAMMA Group)

•Beta firmware released

•New firmware will be releasedsoon

•Integration with software underway

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SRS ATCA card overview

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RTM I/O card:

2 x 8 SFP+ ports

2 x Rj45 (DTCC)

2 x NIM (SMA)

Blade main board:

2 x Virtex 6 FPGA (LX130/240)

2 x DDR3

2 x mezzanine ports

2 x Mezzanines

ATCA Zone 2

backplane connectors

ATCA zone 1 power connector

ATCA Zone 3

RTM connector

RTM I/O card v2:

(under design)

2 x 10GbE (SFP+)

2 x 4 SFP+ ports

2 x Rj45 (DTCC)

2 x NIM (SMA)

$C:\Documents\Dropbox\smartonero\Dropbox\SRS Documents\ATCA-SRS\img\atca_1ss.png$

ATCA-SRS Specifications

Full-mesh backplane connectivity

•Board-to-board connections

•14 x 8 LVDS (13 x 9,6 Gbps – low latency))

Rear Transition Module

•Optional connection to outside world

•2 x 8 GTX (2 x 40(50)Gbps)

–Ethernet, Infiniband, Slink,…

–2 x 10 GbE + 4 x SFP+ under design

•2 x DTCC link (4xLVDS - RD51 specificdata, trigger, clock and control link)

Hub Backplane Connection (CH0)

•4 x GTX versatile connection

–2 x each FPGA

–4 x 1 (Master) FPGA

•Custom protocol (eg. HS-DTCC), 10GbE,Infiniband, …

•40 GbE possible with V7 upgrade

•8

8 GTX

•50 LVDS I/O

•16 SE

•2 LVDS CLKS (from PLL)

Power:

2.5V

3.3V

12V

Management

Low Latency LinksMezzanine Interface

Samtec QTE/QSE Connector

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Low Latency LinksOverview

Inter-FPGA link

• 8 x LVDS (upgradable)

• 2 x GTX

Full-mesh backplane connectivity

•Board-to-board connections

•14 x 8 LVDS

Mezzanine interface

• 50 x LVDS

• 8 x GTX

Mezzanine interface

• 50 x LVDS

• 8 x GTX

$C:\Documents\Dropbox\smartonero\Dropbox\SRS Documents\ATCA-SRS\img\atca_1ss.png$

Low Latency LinksTimings

Inter-FPGA link

• 8 x LVDS (upgradable)

~ 15 ns (using SelectIO circuitry)

Full-mesh backplane connectivity

•15 x 8 LVDS

~ 15 ns (using SelectIO circuitry)

Mezzanine interface

• 50 x LVDS

~ 3 ns (eg. 320 MHz)

Mezzanine interface

• 50 x LVDS

~ 3 ns

*Measurements under way at IFIN-HH

ATCA-SRS Upgrade Path

•EicSys Gmbh is already working on an upgradedesign driven by RD51 members applications(deadline Sept.-Oct. 14)

•Discussions with Eicsys on going regarding NSWapplication

•Two possible upgrade scenarios for NSW TriggerProcessor application:

–A) Replace V6 on blade with V7

–B) Put V7 on mezzanine and upgrade V6 on blade toK7 or a smaller V7

ATCA-SRS Trigger Processor

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OPTO

OPO

OPTO

MEZZANINE

(V7)

FPGA

OPTO

OPO

OPTO

MEZZANINE

(V7)

FPGA

Track results

To/fromneighbor card

To monitoringswitch (eg. 10GbE)

V7 – Track findingalgorithm

K7/V7 – combine sTGC/MMresults + Monitoring,Management, etc,.

To Sector Logic

$C:\Documents\Dropbox\smartonero\Dropbox\SRS Documents\ATCA-SRS\img\atca_1ss.png$

OPTO

OPO

OPTO

MEZZANINE

(V7)

FPGA

OPTO

OPO

OPTO

MEZZANINE

(V7)

FPGA

Track results

To/fromneighbor card

To monitoringswitch (eg. 10GbE)

V7 – Track finding algorithm& combine results +

To Sector Logic

ATCA-SRS Upgrade Schedule and cost

•Current cost/blade: ~3k EUR (based on one full crateorder, i.e. 14 blades)

•Upgrade cost driven mainly by the FPGA cost

•Variant B

–Schedule ~ 12 weeks delivery for prototypes (Eicsys)

–V7 mezzanine proto design by IFIN-HH (see backup)

–Discussion: perhaps we may find a way to integrate the LArAMC design

•Variant A may take longer

Backup

Related developments at IFIN-HH

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SFP+ Mezzanine

advanced design at IFIN-HH/CERN

•8 x SFP+

•up to 25 Gbps (RX/TX)

High Density Optical Mezzanine

Under definition at IFIN-HH

•MiniPods

•V7 (?)