No Slide Title

EE141

© Digital Integrated Circuits2nd

Introduction

1

EE5780 AdvancedVLSI Computer-Aided DesignEE5780 AdvancedVLSI Computer-Aided Design

wetorangeSmall

Dr. Shiyan Hu

Office: EERC 518

Adapted and modified from Digital Integrated Circuits: A Design Perspective

by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

IntroductionIntroduction

EE141

© Digital Integrated Circuits2nd

Introduction

Class Time and Office HourClass Time and Office Hour

Class Time: MWF 14:05-14:55 (EERC 216)

Office Hours: MWF 15:00-15:50 or by appointment, office:EERC 518

Textbook (suggested)

Handbook of Algorithms for Physical Design Automation, Charles J. Alpert,Dinesh P. Mehta, Sachin S. Sapatnekar, CRC Press, 2008

Grading:

Homework 25%

Project 25%

Exams 50%

2

EE141

© Digital Integrated Circuits2nd

Introduction

Course WebsiteCourse Website

http://www.ece.mtu.edu/faculty/shiyan/EE5780Spring12.htm

Contact information of instructor

Email: shiyan@mtu.edu

EERC 518

Instructor’s webpage: http://www.ece.mtu.edu/faculty/shiyan

3

EE141

© Digital Integrated Circuits2nd

Introduction

4

IntroductionIntroduction

Why is designingdigital ICs differenttoday than it wasbefore?

What is thechallenge?

wetorangeSmall

EE141

© Digital Integrated Circuits2nd

Introduction

The Transistor Revolution

First transistor

Bell Labs, 1948

$\\Plume\USERS\bushnell\vlsidesign\pointcontact.jpg$

EE141

© Digital Integrated Circuits2nd

Introduction

The First Integrated Circuit

First IC

Jack Kilby

Texas Instruments

1958

$\\Plume\USERS\bushnell\vlsidesign\firstIC.jpg$

EE141

© Digital Integrated Circuits2nd

Introduction

7

Intel 4004 Microprocessor Intel 4004 Microprocessor

1971

1000 transistors

1 MHz operation

EE141

© Digital Integrated Circuits2nd

Introduction

Intel 8080 Microprocessor

$\\Plume\USERS\bushnell\vlsidesign\intel8080.jpg$

1974

4500 transistors

EE141

© Digital Integrated Circuits2nd

Introduction

9

Intel Pentium Microprocessor

PentiumII

2000

42 million transistors

1.5 GHz

EE141

© Digital Integrated Circuits2nd

Introduction

Modern ChipModern Chip

EE141

© Digital Integrated Circuits2nd

Introduction

11

Basic Components In VLSI CircuitsBasic Components In VLSI Circuits

Devices

Transistors

Logic gates and cells

Function blocks

Interconnects

Local interconnects

Global interconnects

Clock interconnects

Power/ground nets

EE141

© Digital Integrated Circuits2nd

Introduction

CMOS transistorsCMOS transistors

ch02-A12

ch02-A12

3 terminals in CMOS transistors:

 G: Gate

 D: Drain

 S: Source

nMOS transistor/switch X=1 switch closes (ON) X=0 switch opens (OFF)

pMOS transistor/switch X=1 switch opens (OFF) X=0 switch closes (ON)

EE141

© Digital Integrated Circuits2nd

Introduction

An Example: CMOS InverterAn Example: CMOS Inverter

X

X’F =X’

Logic symbol

X

X’F =X’

+Vdd

GRD

Transistor-level schematic

Operation:

 X=1  nMOS switch conducts (pMOS is open) and draws from GRD  F=0

 X=0  pMOS switch conducts (nMOST is open) and draws from +Vdd  F=1

EE141

© Digital Integrated Circuits2nd

Introduction

14

Cross-Section of A ChipCross-Section of A Chip

EE141

© Digital Integrated Circuits2nd

Introduction

15

Moore’s LawMoore’s Law

lIn 1965, Gordon Moore noted that thenumber of transistors on a chip doubledevery 18 to 24 months.

lHe made a prediction thatsemiconductor technology will double itseffectiveness every 18 months

lNot true any more

lInterconnect delay dominates

lVariations

EE141

© Digital Integrated Circuits2nd

Introduction

16

Moore’s law in MicroprocessorsMoore’s law in Microprocessors

4004

8008

8080

8085

8086

286

386

486

Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970

1980

1990

2000

2010

Year

Transistors (MT)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 years

Transistors on Lead Microprocessors double every 2 years

Courtesy, Intel

EE141

© Digital Integrated Circuits2nd

Introduction

17

ITRS Prediction

EE141

© Digital Integrated Circuits2nd

Introduction

18

FrequencyFrequency

P6

Pentium ® proc

486

386

286

8086

8085

8080

8008

4004

0.1

1

10

100

1000

10000

1970

1980

1990

2000

2010

Year

Frequency (Mhz)

Lead Microprocessors frequency doubles every 2 years

Lead Microprocessors frequency doubles every 2 years

Doubles every2 years

Courtesy, Intel

Not trueany more!

EE141

© Digital Integrated Circuits2nd

Introduction

19

0.18

interconnect gif

Source: Gordon Moore, Chairman Emeritus, Intel Corp.

0

50

100

150

200

250

300

Technology generation (m)

Delay (psec)

Transistor/Gate delay

Interconnect delay

0.8

0.5

0.25

0.25

0.15

0.35

Interconnects DominateInterconnects Dominate

EE141

© Digital Integrated Circuits2nd

Introduction

20

Power DissipationPower Dissipation

P6

Pentium ® proc

486

386

286

8086

8085

8080

8008

4004

0.1

1

10

100

1971

1974

1978

1985

1992

2000

Year

Power (Watts)

Lead Microprocessors power continues to increase

Lead Microprocessors power continues to increase

Courtesy, Intel

EE141

© Digital Integrated Circuits2nd

Introduction

21

Power is a major problemPower is a major problem

5KW

18KW

1.5KW

500W

4004

8008

8080

8085

8086

286

386

486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971

1974

1978

1985

1992

2000

2004

2008

Year

Power (Watts)

Power delivery and dissipation will be prohibitive

Power delivery and dissipation will be prohibitive

Courtesy, Intel

EE141

© Digital Integrated Circuits2nd

Introduction

22

Power densityPower density

4004

8008

8080

8085

8086

286

386

486

Pentium® proc

P6

1

10

100

1000

10000

1970

1980

1990

2000

2010

Year

Power Density (W/cm2)

Hot Plate

Nuclear

Reactor

Rocket

Nozzle

Courtesy, Intel

EE141

© Digital Integrated Circuits2nd

Introduction

Chip ThermalChip Thermal

23

EE141

© Digital Integrated Circuits2nd

Introduction

24

System Specification

Functional Design

Logic Design andSynthesis

e.g., Verilog

X=(AB*CD)+(A+D)+(A(B+C))

Y=(A(B+C))+AC+D+A(BC+D))

VLSI Design CycleVLSI Design Cycle

EE141

© Digital Integrated Circuits2nd

Introduction

25

Physical Design

Fabrication

Packaging

VLSI Design Cycle (cont.)VLSI Design Cycle (cont.)

EE141

© Digital Integrated Circuits2nd

Introduction

26

Given a circuit after logic synthesis, to convert it into alayout (i.e., determine the physical location of eachgate and the interconnects between gates).

Physical DesignPhysical Design

PD

EE141

© Digital Integrated Circuits2nd

Introduction

27

Nanoscale ChallengesNanoscale Challenges

Interconnect-limited designs

Interconnect performance limitation

Interconnect modeling complexity

Interconnect reliability (signal integrity)

Power barrier

High degree of on-chip integration

Complexity and productivity

System on a chip

Variations

EE141

© Digital Integrated Circuits2nd

Introduction

28

Robust Design For VariationsRobust Design For Variations

Variations

The difference between the designed value and the actualvalue

Robust design

Mitigate or compensate for variations

Robustness for lithography-induced variations

EE141

© Digital Integrated Circuits2nd

Introduction

29

29

Chip Design and FabricationChip Design and Fabrication

LithographyProcess

Designed ChipLayout

cmp_xsctn_me_gatech_edu

FabricatedChip

EE141

© Digital Integrated Circuits2nd

Introduction

30

30

Photo-Lithography ProcessPhoto-Lithography Process

oxidation

optical

mask

process

step

photoresist coating

photoresist

removal (ashing)

spin, rinse, dry

acid etch

photoresist

stepper exposure

development

Typical operations in a single

photolithographic cycle (from [Fullman]).

EE141

© Digital Integrated Circuits2nd

Introduction

31

31

Lithography SystemLithography System

Illumination

Mask

Objective Lens

Aperture

Wafer

193nmwavelength

45nm

features

EE141

© Digital Integrated Circuits2nd

Introduction

32

32

Mask v.s. PrintingMask v.s. Printing

FeatSizeLimit02-Morph01

0.25µ

FeatSizeLimit02-Morph02

0.18µ

FeatSizeLimit02-Morph03

0.13µ

FeatSizeLimit02-Morph04

90-nm

FeatSizeLimit02-Morph05

65-nm

FeatSizeLimit-Mask

Layout

What youdesign isNOT whatyou get!

EE141

© Digital Integrated Circuits2nd

Introduction

33

33

MotivationMotivation

Chip design cannot be fabricated

Gap

–Lithography technology: 193nm wavelength

–VLSI technology: 45nm features

Lithography induced variations

–Impact on timing and power

lEven for 180nm technology, variations up to 20x inleakage power and 30% in frequency were reported.

Technology nodeTechnology node

130nm130nm

90nm90nm

65nm65nm

45nm45nm

Gate length (nm)Gate length (nm)

Tolerable variation (nm)Tolerable variation (nm)

9090

5.35.3

5353

3.753.75

3535

2.52.5

2828

22

Wavelength (nm)Wavelength (nm)

248248

193193

193193

193193

EE141

© Digital Integrated Circuits2nd

Introduction

34

34

Gap: Lithography Tech. v.s. VLSI Tech.Gap: Lithography Tech. v.s. VLSI Tech.

$C:\Documents and Settings\Shiyan Hu\Desktop\PAINT_BRUSH_.jpg$

FeatSizeLimit-Mask

193nm

28nm, tolerabledistortion: 2nm

Increasing gap Printability problem (andthus variations) moresevere!

EE141

© Digital Integrated Circuits2nd

Introduction

35

SummarySummary

CAD is necessary to design a chip with billiontransistors.

Digital integrated circuit design challenges innanoscale regime

Timing

Power

Reliability

Short design turn-around time