Lecture 2: Parallel Machines Past and Present

Operating Systems & Memory Systems:Address Translation

CPS 220

Professor Alvin R. Lebeck

Fall 2001

CPS 220

Outline

•Address Translation

–basics

–64-bit Address Space

•Managing memory

•OS Performance

Throughout

•Review Computer Architecture

•Interaction with Architectural Decisions

CPS 220

I/O Bus

Core Chip Set

Processor

Cache

Main

Memory

Disk

Controller

Disk

Graphics

Controller

Network

Interface

Graphics

Network

interrupts

System Organization

CPS 220

Computer Architecture

•Interface Between Hardware and Software

Hardware

Software

Operating

System

Compiler

Applications

CPU

Memory

I/O

Multiprocessor

Networks

This is IT

CPS 220

Memory Hierarchy 101

Memory

Very fast 1ns clock

Multiple Instructions

per cycle

SRAM, Fast, Small

Expensive

DRAM, Slow, Big,Cheap

(called physical or main)

=> Cost Effective Memory System (Price/Performance)

Magnetic, Really Slow,

Really Big, Really Cheap

CPS 220

Virtual Memory: Motivation

•Process = AddressSpace + thread(s) ofcontrol

•Address space = PA

–programmer controlsmovement from disk

–protection?

–relocation?

•Linear Address space

–larger than physicaladdress space

»32, 64 bits v.s. 28-bitphysical (256MB)

•Automaticmanagement

Virtual

Physical

CPS 220

Virtual Memory

•Process = virtual address space + thread(s) of control

•Translation

–VA -> PA

–What physical address does virtual address A map to

–Is VA in physical memory?

•Protection (access control)

–Do you have permission to access it?

CPS 220

Virtual Memory: Questions

•How is data found if it is in physical memory?

•Where can data be placed in physical memory?Fully Associative, Set Associative, Direct Mapped

•What data should be replaced on a miss?(Take CPS210 …)

CPS 220

Segmented Virtual Memory

•Virtual address (232, 264) to Physical Address mapping(230)

•Variable size, base + offset, contiguous in both VAand PA

Virtual

Physical

0x1000

0x6000

0x9000

0x0000

0x1000

0x2000

0x11000

CPS 220

Intel Pentium Segmentation

Seg Selector

Offset

Logical Address

Segment

Descriptor

Global Descriptor

Table (GDT)

Segment Base

Address

Physical Address Space

CPS 220

Pentium Segmention (Continued)

•Segment Descriptors

–Local and Global

–base, limit, access rights

–Can define many

•Segment Registers

–contain segment descriptors (faster than load from mem)

–Only 6

•Must load segment register with a valid entry beforesegment can be accessed

– generally managed by compiler, linker, not programmer

CPS 220

Paged Virtual Memory

•Virtual address (232, 264) to Physical Address mapping(228)

–virtual page to physical page frame

•Fixed Size units for access control & translation

Virtual

Physical

0x1000

0x6000

0x9000

0x0000

0x1000

0x2000

0x11000

Virtual page number

Offset

CPS 220

Page Table

•Kernel data structure (per process)

•Page Table Entry (PTE)

–VA -> PA translations (if none page fault)

–access rights (Read, Write, Execute, User/Kernel, cached/uncached)

–reference, dirty bits

•Many designs

–Linear, Forward mapped, Inverted, Hashed, Clustered

•Design Issues

–support for aliasing (multiple VA to single PA)

–large virtual address space

–time to obtain translation

CPS 220

Alpha VM Mapping (Forward Mapped)

•“64-bit” address divided into 3segments

–seg0 (bit 63=0) user code/heap

–seg1 (bit 63 = 1, 62 = 1) user stack

–kseg (bit 63 = 1, 62 = 0)kernel segment for OS

•Three level page table, each onepage

–Alpha 21064 only 43 unique bits of VA

–(future min page size up to 64KB => 55bits of VA)

•PTE bits; valid, kernel & user read& write enable (No reference, use,or dirty bit)

–What do you do for replacement?

base

phys page

frame number

seg 0/1

CPS 220

Inverted Page Table (HP, IBM)

•One PTE per pageframe

–only one VA perphysical frame

•Must search forvirtual address

•More difficult tosupport aliasing

•Force all sharingto use the sameVA

Virtual page number

Offset

VA PA,ST

Hash Anchor Table (HAT)

Inverted Page Table (IPT)

Hash

CPS 220

Intel Pentium Segmentation + Paging

Seg Selector

Offset

Logical Address

Segment

Descriptor

Global Descriptor

Table (GDT)

Segment Base

Address

Linear Address Space

Page

Dir

Physical

Address Space

Dir

Offset

Table

Page

Table

CPS 220

The Memory Management Unit (MMU)

•Input

–virtual address

•Output

–physical address

–access violation (exception, interrupts the processor)

•Access Violations

–not present

–user v.s. kernel

–write

–read

–execute

CPS 220

Translation Lookaside Buffers (TLB)

•Need to perform address translation on everymemory reference

–30% of instructions are memory references

–4-way superscalar processor

–at least one memory reference per cycle

•Make Common Case Fast, others correct

•Throw HW at the problem

•Cache PTEs

CPS 220

Fast Translation: Translation Buffer

•Cache of translated addresses

•Alpha 21164 TLB: 48 entry fully associative

Page

Number

Page

offset

. . .

tag

phys frame

. . .

48:1 mux

. . .

CPS 220

TLB Design

•Must be fast, not increase critical path

•Must achieve high hit ratio

•Generally small highly associative

•Mapping change

–page removed from physical memory

–processor must invalidate the TLB entry

•PTE is per process entity

–Multiple processes with same virtual addresses

–Context Switches?

•Flush TLB

•Add ASID (PID)

–part of processor state, must be set on context switch

CPS 220

Hardware Managed TLBs

•Hardware HandlesTLB miss

•Dictates page tableorganization

•Compilicated statemachine to “walkpage table”

–Multiple levels forforward mapped

–Linked list for inverted

•Exception only ifaccess violation

Control

Memory

TLB

CPU

CPS 220

Software Managed TLBs

•Software HandlesTLB miss

•Flexible page tableorganization

•Simple Hardware todetect Hit or Miss

•Exception if TLBmiss or accessviolation

•Should you checkfor access violationon TLB miss?

Control

Memory

TLB

CPU

CPS 220

Kernel

Mapping the Kernel

•Digital Unix Kseg

–kseg (bit 63 = 1, 62 = 0)

•Kernel has directaccess to physicalmemory

•One VA->PA mappingfor entire Kernel

•Lock (pin) TLB entry

–or special HW detection

User

Stack

Kernel

User

Code/

Data

Physical

Memory

264-1

CPS 220

Considerations for Address Translation

Large virtual address space

•Can map more things

–files

–frame buffers

–network interfaces

–memory from another workstation

•Sparse use of address space

•Page Table Design

–space

–less locality => TLB misses

OS structure

•microkernel => more TLB misses

CPS 220

Address Translation for Large Address Spaces

•Forward Mapped Page Table

–grows with virtual address space

»worst case 100% overhead not likely

–TLB miss time: memory reference for each level

•Inverted Page Table

–grows with physical address space

»independent of virtual address space usage

–TLB miss time: memory reference to HAT, IPT, list search

CPS 220

Hashed Page Table (HP)

•Combine Hash Tableand IPT [Huck96]

–can have more entries thanphysical page frames

•Must search for virtualaddress

•Easier to supportaliasing than IPT

•Space

–grows with physical space

•TLB miss

–one less memory ref thanIPT

Virtual page number

Offset

VA PA,ST

Hashed Page Table (HPT)

Hash

CPS 220

Clustered Page Table (SUN)

•Combine benefits ofHPT and Linear [Talluri95]

•Store one base VPN(TAG) and several PPNvalues

–virtual page block number(VPBN)

–block offset

VPBN

Offset

VPBN

PA0 attrib

Hash

Boff

VPBN

PA0 attrib

...

PA1 attrib

PA2 attrib

PA3 attrib

VPBN

PA0 attrib

VPBN

PA0 attrib

CPS 220

Reducing TLB Miss Handling Time

•Problem

–must walk Page Table on TLB miss

–usually incur cache misses

–big problem for IPC in microkernels

•Solution

–build a small second-level cache in SW

–on TLB miss, first check SW cache

»use simple shift and mask index to hash table

CPS 220

Next Time

•More TLB issues

•Virtual Memory & Caches

•Multiprocessor Issues

Operating Systems & Memory Systems:Managing the Memory System

CPS 220

Professor Alvin R. Lebeck

CPS 220

Review: Address Translation

•Map from virtual address to physical address

•Page Tables, PTE

–va->pa, attributes

–forward mapped, inverted, hashed, clustered

•Translation Lookaside Buffer

–hardware cache of most recent va->pa translation

–misses handled in hardware or software

•Implications of larger address space

–page table size

–possibly more TLB misses

•OS Structure

–microkernels -> lots of IPC -> more TLB misses

CPS 220

Cache Memory 102

•Block 7 placed in 4block cache:

–Fully associative,direct mapped, 2-wayset associative

–S.A. Mapping = BlockNumber ModuloNumber Sets

–DM = 1-way Set Assoc

•Cache Frame

–location in cache

•Bit-selection

7 mod 4

7 mod 2

Set

Main

Memory

CPS 220

Cache Indexing

•Tag on each block

–No need to check index or block offset

•Increasing associativity shrinks index, expands tag

Fully Associative: No index

Direct-Mapped: Large index

Block offset

Block Address

TAG

Index

CPS 220

Address Translation and Caches

•Where is the TLB wrt the cache?

•What are the consequences?

•Most of today’s systems have more than 1 cache

–Digital 21164 has 3 levels

–2 levels on chip (8KB-data,8KB-inst,96KB-unified)

–one level off chip (2-4MB)

•Does the OS need to worry about this?

Definition:

page coloring = careful selection of va->pa mapping

CPS 220

TLBs and Caches

CPU

TLB

MEM

Conventional

Organization

CPU

TLB

MEM

Virtually Addressed Cache

Translate only on miss

Alias (Synonym) Problem

CPU

TLB

MEM

Tags

L2 $

CPS 220

Virtual Caches

•Send virtual address to cache. Called VirtuallyAddressed Cache or just Virtual Cache vs.Physical Cache or Real Cache

•Avoid address translation before accessing cache

–faster hit time to cache

•Context Switches?

–Just like the TLB (flush or pid)

–Cost is time to flush + “compulsory” misses from empty cache

–Add process identifier tag that identifies process as well as addresswithin process: can’t get a hit if wrong process

•I/O must interact with cache

CPS 220

I/O Bus

Memory Bus

Processor

Cache

Main

Memory

Disk

Controller

Disk

Graphics

Controller

Network

Interface

Graphics

Network

interrupts

I/O and Virtual Caches

I/O Bridge

Virtual

Cache

Physical

Addresses

I/O is accomplished

with physical addresses

DMA

• flush pages from cache

• need pa->va reverse

translation

• coherent DMA

CPS 220

Aliases and Virtual Caches

•aliases (sometimescalled synonyms);Two differentvirtual addressesmap to samephysical address

•But, but... thevirtual address isused to index thecache

•Could have data intwo differentlocations in thecache

Kernel

User

Stack

Kernel

User

Code/

Data

Physical

Memory

264-1

CPS 220

•If index is physical part of address, can start tagaccess in parallel with translation so that cancompare to physical tag

•Limits cache to page size: what if want bigger cachesand use same trick?

–Higher associativity

–Page coloring

Index with Physical Portion of Address

Page Address

Page Offset

Address Tag

Index

Block Offset

CPS 220

Page Coloring for Aliases

•HW that guarantees that every cache frame holdsunique physical address

•OS guarantee: lower n bits of virtual & physical pagenumbers must have same value; if direct-mapped,then aliases map to same cache frame

–one form of page coloring

Page Address

Page Offset

Address Tag

Index

Block Offset

CPS 220

Virtual Memory and Physically Indexed Caches

•Notion of bin

–region of cache that maycontain cache blocks froma page

•Random vs carefulmapping

•Selection of physicalpage frame dictatescache index

•Overall goal is tominimize cache misses

Cache

Page frames

CPS 220

Careful Page Mapping

[Kessler92, Bershad94]

•Select a page frame such that cache conflict missesare reduced

–only choose from available pages (no replacement induced)

•static

–“smart” selection of page frame at page fault time

•dynamic

–move pages around

CPS 220

Page Coloring

•Make physical index match virtual index

•Behaves like virtual index cache

–no conflicts for sequential pages

•Possibly many conflicts between processes

–address spaces all have same structure (stack, code, heap)

–modify to xor PID with address (MIPS used variant of this)

•Simple implementation

•Pick abitrary page if necessary

CPS 220

Bin Hopping

•Allocate sequentially mapped pages (time) tosequential bins (space)

•Can exploit temporal locality

–pages mapped close in time will be accessed close in time

•Search from last allocated bin until bin with availablepage frame

•Separate search list per process

•Simple implementation

CPS 220

Best Bin

•Keep track of two counters per bin

–used: # of pages allocated to this bin for this address space

–free: # of available pages in the system for this bin

•Bin selection is based on low values of used and highvalues of free

•Low used value

–reduce conflicts within the address space

•High free value

–reduce conflicts between address spaces

CPS 220

Hierarchical

•Best bin could be linear in # of bins

•Build a tree

–internal nodes contain sum of child <used,free> values

•Independent of cache size

–simply stop at a particular level in the tree

CPS 220

Benefit of Static Page Coloring

•Reduces cache misses by 10% to 20%

•Multiprogramming

–want to distribute mapping to avoid inter-address space conflicts

CPS 220

Dynamic Page Coloring

•Cache Miss Lookaside (CML) buffer [Bershad94]

–proposed hardware device

•Monitor # of misses per page

•If # of misses >> # of cache blocks in page

–must be conflict misses

–interrupt processor

–move a page (recolor)

•Cost of moving page << benefit

CPS 220

Outline

•Page Coloring

•Page Size

CPS 220

A Case for Large Pages

•Page table size is inversely proportional to the pagesize

–memory saved

•Fast cache hit time easy when cache <= page size (VAcaches);

–bigger page makes it feasible as cache size grows

•Transferring larger pages to or from secondarystorage, possibly over a network, is more efficient

•Number of TLB entries are restricted by clock cycletime,

–larger page size maps more memory

–reduces TLB misses

CPS 220

A Case for Small Pages

•Fragmentation

–large pages can waste storage

–data must be contiguous within page

•Quicker process start for small processes(??)

CPS 220

Superpages

•Hybrid solution: multiple page sizes

–8KB, 16KB, 32KB, 64KB pages

–4KB, 64KB, 256KB, 1MB, 4MB, 16MB pages

•Need to identify candidate superpages

–Kernel

–Frame buffers

–Database buffer pools

•Application/compiler hints

•Detecting superpages

–static, at page fault time

–dynamically create superpages

•Page Table & TLB modifications