ECE 477 Design ReviewTeam 3 Fall 2007ECE 477 Design ReviewTeam 3 Fall 2007
Steven
Kingsley
(Analog)
Roy
Scheck
(Leader)
Tony
Liechty
(Digital)
Charles
Lan
(Software)
OutlineOutline
•Project overview•Project overview
•Project-specific success criteria•Project-specific success criteria
•Block diagram•Block diagram
•Component selection rationale•Component selection rationale
•Packaging design•Packaging design
•Schematic and theory of operation•Schematic and theory of operation
•PCB layout•PCB layout
•Software design/development status•Software design/development status
•Project completion timeline•Project completion timeline
•Questions / discussion•Questions / discussion
Project OverviewProject Overview
•Allows a single note instrument to be usedas a MIDI instrument•Allows a single note instrument to be usedas a MIDI instrument
•Ability to tune the instrument for moreaccurate MIDI conversion•Ability to tune the instrument for moreaccurate MIDI conversion
•MIDI is an audio standard•MIDI is an audio standard
•Software allows real time composition ofmusic from MIDI•Software allows real time composition ofmusic from MIDI
Project-Specific Success CriteriaProject-Specific Success Criteria
1.Ability to detect the fundamental frequency of anote from a single note instrument through ananalog microphone.1.Ability to detect the fundamental frequency of anote from a single note instrument through ananalog microphone.
2.Ability to determine/guess the “closest note” beingplayed based on the fundamental frequencydetected (in 1 above).2.Ability to determine/guess the “closest note” beingplayed based on the fundamental frequencydetected (in 1 above).
3.An ability to calculate “how far off” (out-of-tune) thenote being played is relative to the intended“nearest note” (determined in 2 above).3.An ability to calculate “how far off” (out-of-tune) thenote being played is relative to the intended“nearest note” (determined in 2 above).
4.Ability to communicate note information to acomputer.4.Ability to communicate note information to acomputer.
5.Ability to display note detection/operational statususing an LCD display.5.Ability to display note detection/operational statususing an LCD display.
Block DiagramBlock Diagram
PreAmp
Filter
Microphone
DSP
LCD
USB interface
ATD
Volume Control
Parallel
GPIO
2
SPI
7
I2C
4
Volume
Knob
2
PWM
GPIO
Component Selection RationaleComponent Selection Rationale
•DSP requirements•DSP requirements
•1 ATD converter•1 ATD converter
•At least 8 bits for sufficient resolution•At least 8 bits for sufficient resolution
•SPI interface for SPI to USB controller•SPI interface for SPI to USB controller
•I2C for digital potentiometer•I2C for digital potentiometer
•PWM for analog filter•PWM for analog filter
•7 GPIO pins for parallel LCD interface•7 GPIO pins for parallel LCD interface
•~1200 bytes of RAM for sampling•~1200 bytes of RAM for sampling
•10Mhz Clock for proper resolution•10Mhz Clock for proper resolution
Component Selection RationaleComponent Selection Rationale
•Possible DSPs•Possible DSPs
–Freescale 56F8014–Freescale 56F8014
•16 Kbyte flash, 4 Kbyte RAM•16 Kbyte flash, 4 Kbyte RAM
•32 Mhz Clock, 32 pins•32 Mhz Clock, 32 pins
•$3.15 in 1,000 quantities•$3.15 in 1,000 quantities
–Atmel AT32UC3B164–Atmel AT32UC3B164
•64 Kbyte flash, 16 Kbyte RAM•64 Kbyte flash, 16 Kbyte RAM
•90 Mhz Clock, 48 pins•90 Mhz Clock, 48 pins
•$4.66 in 10,000 quantities•$4.66 in 10,000 quantities
•Newer•Newer
Component Selection RationaleComponent Selection Rationale
•DSP•DSP
–Freescale 56F8014 ($3.15)–Freescale 56F8014 ($3.15)
•32 total pins•32 total pins
•Two 12-bit ATDs•Two 12-bit ATDs
•SPI, SCI, I2C, PWM•SPI, SCI, I2C, PWM
•21 GPIO•21 GPIO
•16 Kb flash, 4 Kb RAM•16 Kb flash, 4 Kb RAM
•32 Mhz Clock•32 Mhz Clock
•4 pin JTAG/OnCE Interfacefor programming•4 pin JTAG/OnCE Interfacefor programming
Component Selection RationaleComponent Selection Rationale
•USB Controller•USB Controller
–MAX3421E ($2.65)–MAX3421E ($2.65)
•USB Peripheral Controllerwith SPI Interface•USB Peripheral Controllerwith SPI Interface
•Allows anymicrocontroller with SPIto be connected overUSB•Allows anymicrocontroller with SPIto be connected overUSB
•2 GPIO for Volume Knob•2 GPIO for Volume Knob
–Easier Routing–Easier Routing
–Accessed through SPI–Accessed through SPI
Component Selection RationaleComponent Selection Rationale
•LCD•LCD
–CFAH1602B-YTI-JP–CFAH1602B-YTI-JP
•4 bit parallel interface (4 pins)•4 bit parallel interface (4 pins)
•3 bit functionality (3 pins)•3 bit functionality (3 pins)
•Power consumption•Power consumption
–1.5 ma for LCD–1.5 ma for LCD
–150 ma for Backlight–150 ma for Backlight
Packaging DesignPackaging Design
•Form Factor•Form Factor
–Small for mobility–Small for mobility
–Sloped panel for easy viewing and bettermicrophone reception–Sloped panel for easy viewing and bettermicrophone reception
•Packaging Features•Packaging Features
–LCD display of Note Information and Volume–LCD display of Note Information and Volume
–Incoming Signal Amplifier (Rotary Knob)–Incoming Signal Amplifier (Rotary Knob)
–Internal Microphone–Internal Microphone
–USB Interface (Female “B” Adapter)–USB Interface (Female “B” Adapter)
Packaging DesignPackaging Design
•Hammond 1456CE2•Hammond 1456CE2
Schematic/Theory of OperationSchematic/Theory of Operation
PreAmp
Filter
Microphone
DSP
LCD
USB interface
ATD
Volume Control
D+
D-
Parallel
GPIO
2
SPI
7
I2C
4
Volume
Knob
2
PWM
GPIO
Schematic/Theory of OperationSchematic/Theory of Operation
•Power Supplies (3.3V, 1 Amp)•Power Supplies (3.3V, 1 Amp)
–Separate Analog and Digital supplies–Separate Analog and Digital supplies
Schematic/Theory of OperationSchematic/Theory of Operation
•Analog•Analog
–Amplify and Bias at 1.65V–Amplify and Bias at 1.65V
–Filter–Filter
10 mV
-10 mV
0 V
3 V
0 V
Schematic/Theory of OperationSchematic/Theory of Operation
Filter
Digital Potentiometer
AmplifierAmplifier
Schematic/Theory of OperationSchematic/Theory of Operation
Digital PotentiometerDigital Potentiometer
Amplifier
DSP
ATD
GPIO
SPI
I2C
PWM
PWM
Schematic/Theory of OperationSchematic/Theory of Operation
Amplifier
DSP
ATD
GPIO
SPI
I2C
PWM
FilterFilter
PWM
Schematic/Theory of OperationSchematic/Theory of Operation
USB interface
D+
D-
LCD
Parallel
OnCE
Volume Control
Filter
Clock
Interrupt
DSP
Schematic/Theory of OperationSchematic/Theory of Operation
DSP
ATD
GPIO
SPI
I2C
PWM
PWM
SPI To USB
Schematic/Theory of OperationSchematic/Theory of Operation
DSP
ATD
GPIO
SPI
I2C
PWM
PWM
Ground
Header
PCB LayoutPCB Layout
•General DesignConsiderations•General DesignConsiderations
•Specific DesignConsiderations•Specific DesignConsiderations
–Power Supply–Power Supply
–Analog–Analog
–Digital–Digital
PCB LayoutPCB Layout
•General DesignConsiderations•General DesignConsiderations
–Overall low powerconsumption–Overall low powerconsumption
•General tracewidth of 10 mils•General tracewidth of 10 mils
–Separate Analog andDigital systems–Separate Analog andDigital systems
–Minimize trace length–Minimize trace length
–Minimize angles–Minimize angles
PCB LayoutPCB Layout
•Power Supply DesignConsiderations•Power Supply DesignConsiderations
–Separate Analog andDigital–Separate Analog andDigital
•Separate Grounds•Separate Grounds
–5 V Unregulated Supply–5 V Unregulated Supply
•Trace width of 80 mils•Trace width of 80 mils
–3.3 V Regulated Supply–3.3 V Regulated Supply
•Trace width of 70 mils•Trace width of 70 mils
–Bypass Capacitors–Bypass Capacitors
•Placed directlybeneath VoltageRegulators•Placed directlybeneath VoltageRegulators
PCB LayoutPCB Layout
•Analog DesignConsiderations•Analog DesignConsiderations
–High sensitivity–High sensitivity
•Ground shielding•Ground shielding
•Copper Pour•Copper Pour
–Microphone–Microphone
•Minimize leads•Minimize leads
–Bypass Capacitors–Bypass Capacitors
•Placed directlybeneathrespective IC•Placed directlybeneathrespective IC
PCB LayoutPCB Layout
•Digital DesignConsiderations•Digital DesignConsiderations
–Bypass Capacitors–Bypass Capacitors
•Placed directlybeneathMicrocontroller•Placed directlybeneathMicrocontroller
–Bulk Capacitors–Bulk Capacitors
•Placed further fromMicrocontroller•Placed further fromMicrocontroller
–General Purpose I/O Pins–General Purpose I/O Pins
•Assigned tocorresponding side tominimize length•Assigned tocorresponding side tominimize length
Software Design/Development StatusSoftware Design/Development Status
•Three options for development•Three options for development
–JTAG/OnCE–JTAG/OnCE
•Easy to debug•Easy to debug
•Costly Development board•Costly Development board
–SCI serial bootloader–SCI serial bootloader
•Frees up more pins•Frees up more pins
•Addition of level translators and RS232implementation•Addition of level translators and RS232implementation
–Bulk device programmer–Bulk device programmer
•Hard to debug after packaging•Hard to debug after packaging
•Easy to program multiple chips•Easy to program multiple chips
Software Design/DevelopmentStatusSoftware Design/DevelopmentStatus
•Frequency Detection•Frequency Detection
–Zero-crossings(currently favoredapproach)–Zero-crossings(currently favoredapproach)
–Peak counting–Peak counting
–Hybrid model–Hybrid model
–Shift/Compare–Shift/Compare
•Simulations run in C++using DirectSound•Simulations run in C++using DirectSound
Project Completion TimelineProject Completion Timeline
Week #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PCB
Assembly of PCB
Software
Packaging
Testing
Documentation
Research
Schematic
Project Finalization
Thanksgiving
Current Week
Questions / DiscussionQuestions / Discussion
