1
2
Figure 2.1 Latches, flip-flops, and registers.
2.1 Latches, Flip-Flops, and Registers
3
Figure 2.2 Operations of D latch and negative-edge-triggered D flip-flop.
The required stability time for D before the falling edge is known as setuptime, while that after the falling edge is hold time.
4
Figure 2.3 Register-to-register operation with edge-triggered flip-flops.
Interconnection of registers and combinationalcomponents in synchronous sequential system.
5
•FSM: A model of computation consisting of a set ofstates, input symbols, and a transition function thatmaps input symbols and current states to a next state.
•State Table: The state table representation of a sequentialcircuit consists of three sections labelled present state, nextstate and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next stateshows the states of flip-flops after the clock pulse, and theoutput section lists the value of the output variables during thepresent state.
•State Diagram: In addition to graphical symbols, tables orequations, flip-flops can also be represented graphically by astate diagram. In this diagram, a state is represented by a circle,and the transition between states is indicated by directed lines(or arcs) connecting the circles.
2.2 Finite-State Machine (FSM)
6
State Machines: Definition of Terms
•State Diagram
–Illustrates the form and functionof a state machine. Usuallydrawn as a bubble-and-arrowdiagram.
•State
–A uniquely identifiable set ofvalues measured at variouspoints in a digital system.
•Next State
–The state to which the statemachine makes the nexttransition, determined by theinputs present when the device isclocked.
•Branch
–A change from presentstate to next state.
•Mealy Machine
–A state machine thatdetermines its outputs fromthe present state and theinputs.
•Moore Machine
–A state machine thatdetermines its outputs fromthe present state only.
7
Figure 2.4 State table and state diagram for a vending machine coin reception unit.
Example 2.1Coin Reception State Machine
8
2.3 Designing a sequential circuits
General steps:
•(sometimes) draw a transition network for the circuit
•build a transition table
•use the transition table as the truth table for the "next state"combinatorial circuit
•convert this table to a circuit
•if necessary, build an output function truth table and convert itto a circuit
•example: binary up-counter; binary up-down counter
•example: "traffic light" circuit from text
9
Figure 2.5 Hardware realization of Moore and Mealy sequential machines.
Moore Machine: Outputs are derived only based onstate variables.
Mealy Machine: Outputs depends on both presentstate and the current inputs.
10
Example 2.2 Building a JK-FF with D-FF
J K
Q+
0 0
Q
0 1
0
1 0
1
1 1
Q’
Step 1: Derive the state table
Step 2: state minimization
11
Q: present state, Q+: next state
0
1
JK=0x
x0
1x
x1
Step 3: apply state assignment
There are two states. One FF is enough. Here D-FF is chosen.
Step 4: Form the excitation table of the circuit.
J K
Q
Q+
D
0 x
0
0
0
1 x
0
1
1
x 1
1
0
0
x 0
1
1
1
12
Step 5: Form the minimized excitation and outputfunctions
0
0
1
1
1
0
0
1
JK
00 01 11 10
Q
0
1
D
13
Figure 2.6 Hardware realization of a JK flip-flop (Example 2.2).
14
Table 2.2 State table for a coin reception unit after the state assignment chosen in Example 2.3.
Example 2.3 Sequential circuit for a coin reception
Step 1: Derive the state table (see Example 2.1 on p24)
Step 2: state minimization (S25 and S30 are merged intoone state S25/S30)
Step 3: apply state assignment
There are five states, it needs 3 FFs. Here we use D-FFs.
15
Step 4: Form the excitation table of the circuit
q d
Q2Q1Q0
Q2+Q1+Q0+
D2D1D0
0 0
0 0 0
0 0 0
0 0 0
0 0
0 0 1
0 0 1
0 0 1
0 0
0 1 0
0 1 0
0 1 0
0 0
0 1 1
0 1 1
0 1 1
0 0
1 x x
1 x x
1 x x
0 1
0 0 0
0 0 1
0 0 1
0 1
0 0 1
0 1 0
0 1 0
0 1
0 1 0
0 1 1
0 1 1
0 1
0 1 1
1 x x
1 x x
0 1
1 x x
1 x x
1 x x
q d
Q2Q1Q0
Q2+Q1+Q0+
D2D1D0
1 0
0 0 0
0 1 1
0 1 1
1 0
0 0 1
1 x x
1 x x
1 0
0 1 0
1 x x
1 x x
1 0
0 1 1
1 x x
1 x x
1 0
1 x x
1 x x
1 x x
1 1
0 0 0
x x x
x x x
1 1
0 0 1
x x x
x x x
1 1
0 1 0
x x x
x x x
1 1
0 1 1
x x x
x x x
1 1
1 x x
x x x
x x x
16
Five-Variable K-Map (Karnaugh-map)
Q1Q0
qd
00
01
11
10
00
0
0
x
0
01
0
0
x
1
11
0
1
x
1
10
0
0
x
1
00
1
1
x
1
01
1
1
x
1
11
1
1
x
1
10
1
1
x
1
Q1Q0
qd
00
01
11
10
Q2 = 1
Q2 = 0
D2
17
Five-Variable K-Map
Q1Q0
qd
00
01
11
10
00
0
0
x
1
01
0
1
x
x
11
1
x
x
x
10
1
1
x
x
00
x
x
x
x
01
x
x
x
x
11
x
x
x
x
10
x
x
x
x
Q1Q0
qd
00
01
11
10
Q2 = 1
Q2 = 0
D1
18
Five-Variable K-Map
Q1Q0
qd
00
01
11
10
00
0
1
x
1
01
1
0
x
x
11
1
x
x
x
10
0
1
x
x
00
x
x
x
x
01
x
x
x
x
11
x
x
x
x
10
x
x
x
x
Q1Q0
qd
00
01
11
10
Q2 = 1
Q2 = 0
D0
19
Figure 2.7 Hardware realization of a coin reception unit (Example 2.3).
Step 5: Form the minimized excitation and output functions
20
Figure 2.8 Register with single-bit left shift and parallel load capabilities. For logical left shift, the serial data in line is connected to 0.
2.4 Useful Sequential Parts --- Shift register
A register is an array of FFs.
21
•Serial to parallel register
•Parallel to serial register
22
Figure 2.9 Register file with random access and FIFO.
Register file: an array of registers
FIFO:
23
Figure 2.10 SRAM memory is simply a large, single-port register file.
SRAM:Single port register file
DRAM?
24
Figure 2.11 Synchronous binary counter with initialization capability.
Counter: Binary counter, BCD counter, Hexadecimal Counter
25
Figure 2.12 Examples of programmable sequential logic.
PAL, FPGA
26
2.6 Clocks and Timing of Events
Clock: a clock is a circuit that produce a periodic signal,usually at a constant frequency or rate. The clock signal is at0 or 1 for about half the clock period.
Clock period tprop+tcomb+tsetup+tskew
27
Figure 2.14 Synchronizers are used to prevent timing problems that might otherwise arise from untimely changes in asynchronous signals.
Asynchronous input, synchronozer
28
Figure 2.15 Two-phase clocking with nonoverlapping clock signals.
Two-phase clocking