Work Package 3 On-detector Power ManagementSchemesESR Michal Bochenek
ACEOLE Twelve Month Meeting
1st October 2009
WPL Jan Kaplon
Aim of work
Development of new, efficient powerdistribution schemes allowing for majorreduction of amount of material inside theparticle detectors
•DC-DC conversion technique
•serial powering scheme
Objective; development of radiation-tolerantASIC building blocks for upgraded front endelectronics for ATLAS SCT
ABCN, a prototype chip for Si stripreadout in Upgrade Inner Tracker
Binary readout
Front-end optimised for shortstrips
Positive or negative input charge
Readout clock up to 160Mbits/sec
250 nm CMOS (IBM) technology
Compatible with serial poweringscheme and DC/DC converters(high filtering efficiency of LinearRegulator)
Analogue supply (2.2V) obtained from 2.5V digital power rail(shunt in case of serial powering or DC-DC converter) by means ofLinear Voltage Regulator
Next step; ABCN in 130 or 90nm
•Motivation; lowering power consumption(lower voltage supply, better noise powerfigure)
•Change in overall voltage supply from 2.5V to1.2V, digital part supply with 0.9V (furtherreduction of power reduction) this implythe change in the currently adopted powerdistribution schemes (both DC-DC and serialapproach)
Possible power schemes for ABCN in130nm, serial powering
vddd
gndd
Vdd(a)
gnda
Fully integratedShunt Regulator
ABCNDigital
ABCNAnaloge
0.9 V
1.2V
Voltage
Regulator
DC-DC
Chargepump
1.5V
Designed by M.Bochenek
ABCN
Possible power schemes for ABCN in130nm, DC-DC approach
2.8V
gnd
DC/DCbuckconverteron module
ABCNDigital
0.9 V
Voltage
Regulator
1.2 V
ABCNAnalog
DC-DC
Step-down/2
2V
gnd
DC/DCbuckconverteron module
DC-DC
Step-down/2
1.4 V
10V
10V
Designed by M.Bochenek
ABCN
Architecture of a step-down DC-DCconverter
The core of the DC-DC step-down converter is
built of four transistors (one PMOS and three NMOS) and three
external SMD capacitors. The whole circuit is supplied
with 2.0 V. Due to the better driving capability of switches, working
with lower output voltage, there is no need to use any level shifters.
The output voltage is as high as 920 mV for a nominal current, which
is 60 mA, but the converter can operate at 100 mA with power
efficiency up to 88 %.
480um
200um
Step-up charge pump
The switched capacitor step-up charge pump shown is based on the voltagedoubler circuit. The main part of the circuit consist of two cross-coupled NMOS transistors (M1 and M2), four PMOS transistorsworking as serial switches (M3 – M6), three external SMD capacitors(CPUMPX and CLOAD) and one capacitor integrated on the chip (Cpol).
The optimized working frequency is around 500kHz.
Due to the poor driving capability of the PMOS serial switches, two levelshifters are needed. Those voltage shifters require two voltagesupplies, the input signal voltage supply (0.9 V) and the output signalvoltage
supply (VOUT = 1.6 V) taken from the output of the charge pump.
Minimum efficiency 84% over a full corner sweep
To be done
•Implementation of the fully integrated shuntdesign from ABCN (250nm) in the 130 nmtechnology (3 possible architectures).
•Implementation of the serial regulator in 130 nm.
•Integration of a complete power managementblocks (DC/DC, shunt, linear regulator) on thefront-end prototype chip.
Summary of on-the-job training
•Training in schematic, simulation and layout tools(CADENCE/SPICE)
•Courses;
–Advanced Engineering Course OPERATIONAL AMPLIFIERS: Theory &Design (10.11.2008 - 13.11.2008, Delft University of Technology, Delft,The Netherlands)
– Adaptive Power Management Course (8.02.2009, ISSCC, SanFrancisco, CA, United States)
– Low-voltage and Mixed Signal CMOS Circuit Design Course(12.02.2009, ISSCC, San Francisco, CA, United States)
–EIROforum School of Instrumentation (ESI) (11.05.2009 - 15.05.2009,CERN, Geneva, Switzerland)
– Low-Power, Low Voltage Analog IC Design (22.06.2009 - 26.06.2009,Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland)
Deliverables
•TC31 (month 6), Training courses in microelectronics design methods,CAD tools, design of circuits for regulators, etc (completed)
–Advanced Engineering Course OPERATIONAL AMPLIFIERS: Theory & Design(10.11.2008 - 13.11.2008, Delft University of Technology, Delft, TheNetherlands)
– Adaptive Power Management Course (8.02.2009, ISSCC, San Francisco, CA,United States)
– Low-voltage and Mixed Signal CMOS Circuit Design Course (12.02.2009,ISSCC, San Francisco, CA, United States)
–Low-Power, Low Voltage Analog IC Design (22.06.2009 - 26.06.2009, EcolePolytechnique Fédérale de Lausanne, Lausanne, Switzerland)
•W31 Participation in TWEPP workshop (completed)
–Paper “An integrated DC-DC step-up charge pump and step-down converter in130 nm technology” presented on Topical Workshop on Electronics forParticle Physics (TWEPP09) (21.09.2009 – 25.09.2009, Paris, France)
Secondment
•The secondment is planned at AGH, University of Science andTechnology, Krakow;
•Preferred duration of the secondment is 3 months at the endof the ESR contract
•Plan of activities anticipated for the secondment:
–Participation in preliminary tests of full ATLAS SCT readout chipsintegrated with the power distribution system designed by theESR during his contract at CERN,
–Preparation of the final report on milestones and deliverablesfor the European Union Committee,
–Passing final obligatory exams before a defence of a doctoralthesis.
Training by Visitor Scientist
A visit of senior scientist from AGH University ofScience and Technology, Krakow is to beorganised.