PowerPoint Presentation

Low Power – High SpeedMCML Circuits (II)

ShahnamKhabiri

95.575

March, 2002

Outline:Outline:

- Introduction

- CSL and MCML operation

- CMOS, MCML, CML, ECL comparison

- DyCML

- Feedback MCML

- Adaptive pipeline system for MCML

- Conclusion

- References

IntroductionIntroduction

VLSI development goals:

- Large integration density

- High speed operation

- Low power dissipation

- Low cost

Introduction …Introduction …

Why not CMOS:

- Switching noise in mixed mode ASIC’s

- f   P 

- Vdd   P , but Delay  , …

Why CMOS:

- High packing densities

- High noise margin

- Simplicity

- No static power dissipation

- Yield

- Low cost, …

Current Steering Logic (CSL)Current Steering Logic (CSL)

$C:\My Documents\shahnam\fig3.JPG$

Advantage:

- Reduced power supply current noise

Disadvantage:

- Additional output branch for each fanout

- Static power dissipation

- Frequency proportional dynamic powerdissipation

$C:\My Documents\shahnam\fig36.JPG$

MCML OperationMCML Operation

- Rise time depends on RL(RFP voltage)

- Fall time depends on I (RFNvoltage)

- NMOS current source haslonger L to provide high ro

- Less sensitivity to noisemargin and gain, therefore :

gain could be set to 1.4

and Vswing set to 300mv

$C:\My Documents\shahnam\fig35.JPG$

MCML Logic GatesMCML Logic Gates

$C:\My Documents\shahnam\fig23.JPG$

CMOS, MCML, CML, ECLCMOS, MCML, CML, ECL

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$C:\My Documents\shahnam\fig6.JPG$

$C:\My Documents\shahnam\fig4.JPG$

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CMOS

MCML

CML

ECL

Delay

C.Vdd/[K(Vdd-VT)2]

C.V/I

<Tcml

Power

C(Vdd)2.f

Vdd.I

>Pcml

Vms

VT = 0.6 v

(I/K)0.5+VT= 0.9 v

2VBE+VSC= 1.8 v

3VBE+VSC= 2.6 v

CMOS, MCML, CML, ECL …CMOS, MCML, CML, ECL …

$C:\My Documents\shahnam\fig30.JPG$

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Simulated results for an MCML F.A.Simulated results for an MCML F.A.

$C:\My Documents\shahnam\fig10.JPG$

- MCML Full Adder in 0.5um

Vdd = 1.2 v

delay = 200ps

-CMOS:

Vdd = 3.3 v, delay = 600ps

Vdd = 1.5 v, delay = 2ns

Experimental results for an MCML F.FExperimental results for an MCML F.F

$C:\My Documents\shahnam\fig11.jpg$

- 0.5 um cmos, f = 1.8 GHz

- Delay between clock edge and output= 160ps

DyCMLDyCML

$C:\My Documents\shahnam\fig12.JPG$

- Vswing.CL = WC1.LC1.Cox.(Vdd-Vswing)

- C1 size

$C:\My Documents\shahnam\fig13.JPG$

Advantage:

- Dynamic current source

- No static power dissipation

- More stability in compare with otherdynamic circuits

- Supply voltage is as low as Vtn+|Vtp|

DyCML …DyCML …

Cascading:

$C:\My Documents\shahnam\fig14.JPG$

1- Clock Delay mechanism (CD)

less stability

2- Self Timing scheme (ST)

higher delay and power consumption

Simulation results for DyCMLSimulation results for DyCML

$C:\My Documents\shahnam\fig15.bmp$

- Using 0.6 um CMOS

- Vdd = 3.3 v, f = 100MHz

- DyCML more suitable forcomplex gates

- ST is slower than CD andconsumes more power

Feedback MCMLFeedback MCML

Effect of Vthfluctuation:

$C:\My Documents\shahnam\fig16.JPG$

$C:\My Documents\shahnam\fig17.JPG$

- Vth fluctuation is due to:

Fluctuation of gate oxidethickness

Fluctuation of gate length

Random placement of thechannel dopant

-VB = G(0).Vth

G(0)  VB

Feedback MCML …Feedback MCML …

$C:\My Documents\shahnam\fig18.JPG$

$C:\My Documents\shahnam\fig19.JPG$

$C:\My Documents\shahnam\fig20.JPG$

- If GC(fmax) = GF(fmax)

 GF(0) < GC(0) 

VB is smaller 

More tolerance forVth @ several GHz

- LMF1 and LMF2 arelarger than minimum

Feedback MCML 1:2 Demux andsimulation results:Feedback MCML 1:2 Demux andsimulation results:

$C:\My Documents\shahnam\fig21.JPG$

$C:\My Documents\shahnam\fig22.JPG$

- Feedback MCMLtolerates two times moreVth fluctuation incompare withconventional MCML

- Experimental resultsshow 10 Gb/s Mux,Demux 1:8 in 0.18umuse ¼ power of GaAs orSi bipolar and faster thanCMOS.

- Feedback MCMLLatch implementation

MCML Optimization in Mixed SignalApplications …MCML Optimization in Mixed SignalApplications …

Voltage Swing Control (VSC):

$C:\My Documents\shahnam\fig24.JPG$

- VSC allows fixed voltageswing across variety ofcurrents and easy trade offspeed for power

- Drawbacks:

Power and area overhead

different gates won’t trackVlow exactly so hard to shareVSC

Adaptive pipeline system for MCMLAdaptive pipeline system for MCML

$C:\My Documents\shahnam\fig25.JPG$

Current SourceController:

- RFN and consequently Iwill be set based oncritical path delayrequirements

- Circuit timinginsensitive to process,temperature and voltagevariation.

- Design for nominaldelay and not the worstcase delay

Full Adder in MCMLFull Adder in MCML

$C:\My Documents\shahnam\fig28.JPG$

- We can use Currentscaling to increase Carryspeed

- For small number ofbits <16 bits CLA is not agreat help

Experimental Results:Experimental Results:

$C:\My Documents\shahnam\fig26.JPG$

- Using 0.25 CMOSprocess for a 12 bitsCORDIC Full Adder

- Power results of MCMLare up to 1.5 times lessthan CMOS CORDIC’swith similar propagation

ConclusionConclusion

- High speed:

Tcmos > Tmcml > Tcml > Tecl

NMOS devices, Low voltage swing, All ON Transistors

- Low power consumption

@500MHz with applicable Vdd’s:

Pcmos > Pecl > Pcml > Pmcml

- Flexible to construct any logic circuit

- High speed compact circuits are feasible

- P is constant with increasing f (good for high speed applications)

- Fixed power supply current (good for mixed signal ASIC’s)

- Vdd  P , No effect on Delay

MCML advantages:

Conclusion …Conclusion …

- Small Vswing reduces cross talk

- Common noise rejection capability

- MOS related advantages:

good yield, small area, low cost, low supply voltage

- No theoretical minimum for E.D

For a linear chain of N identical MCML gates:

E.D = N3.C2.Vdd.V2/I

I  E.D

-Flexibility in design optimization:

Vswing, I, Vdd, Transistor sizes

MCML advantages:

Conclusion …Conclusion …

- VT deviation impact on functionality anddelay

- Static power

- Not suitable for power down mode systems

- Large load resistors need large area

- Matching of rise and fall delays

- Shallow depth logic is a limit for MCML

$C:\My Documents\shahnam\fig8.JPG$

MCML disadvantages:

References:References:

Yamashina, Yamada,”An MOS Current Mode Logic Circuit forLow Power GHz Processors”, NEC Res & Dev, 1995.

J.Rabaey, J.M.Musicer,”MOS current mode logic for low power,low noise CORDIC computation in mixed signal environment”,2000.

A.Tanabe,”0.18 u CMOS 10 Gb/s Multiplexer/Demultiplexer Icsusing current mode logic with tolerance to Threshold Voltagefluctuation”,IEEE J. Solid State Circuits, Vol36, No 6, June2001.

M.W.Allam, M.I.Elmasry,”Dynamic current mode logic: a newlow power high performance logic style”,IEEE J. Solid StateCircuits, Vol36, No 3, March 2001.

D.J.Allostot,”Current mode logic techniques for CMOS mixed-mode ASIC’s”,IEEE Custom Integrated Circuits Conf., 1991.