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A 1-Tap 40-Gbps DecisionFeedback Equalizer in a 0.18-mSiGe BiCMOS Technology
Adesh Garg, Anthony ChanCarusone and Sorin P.Voinigescu
University of Toronto
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Motivation
■Electrical equalization has been found to be an effective way to mitigatePMD limited fibre optical channels
■Linear equalizer can be paired with a decision feedback equalizer (DFE) tofurther extend the transmission range and/or increase the data rates
■State of the art
►FFE demonstrated at speeds over 40-Gbps in silicon
►DFE demonstrated only recently at speeds up to 10-Gbps in 0.13 mCMOS as well as a 0.18 m SiGe BiCMOS
Goal: To design a 1-Tap DFE at 40-Gbps
system_level_DFE
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Architecture
■Direct Feedback – filterprocessing in feedback path
►Disadvantages:
●Multiple processing stages infeedback path
●Additional loading atsumming node
Conceptual_DFE_mulitple_tap
■Look-ahead – parallelcomputation of filter
►Advantages:
●Parallelism employed toremove processing infeedback path
●Limits loading on summingnode
Conceptual_Look_ahead_DFE
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Architecture
■Implementation of thearchitecture requiresconsiderable overheadwithin the clock distribution
■Clock path requires thehighest bandwidth
►Difficult design
►Power intensive
■The retimers are replacedwith slicers at the inputs ofthe selector to easerequirements on the clockdistribution
clock_path_full_chip
ChipArchitecture_block_diag
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ChipArchitecture_design_pre
Circuit Description
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Circuit Description: BroadbandFront End
■Shunt-Series Input Buffer(TIA)
►Shunt feedback allows forbroadband frequencyresponse while matching to50 
►Resistive degeneration (Seriesfeedback) employed tofurther improve inputlinearity
►Allows low noise bias withoutsignificantly limiting bandwidth
broadband_frontend_tia
TIAschematic_presentation
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Circuit Description: BroadbandFront End
■Threshold adjustmentfunctionality
►Transition is“strengthened” withvariable threshold
►Allows detection ofmissed bits
Input
Output
sample_slicing_threshold_0_
ChipArchitecture_block_diag
sample_slicing_threshold_no
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Circuit Description: BroadbandFront End
■ThresholdAdjustment Buffer
►High Speed Buffer
●linearity
►DC offset
●linear tuning withcontrol voltage
►Adjust threshold upto 225mV
broadband_frontend_threshol
Offsetschematic_presentatio
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Circuit Description: DecisionSelective Feedback
DSF_ff
ECL Master Slave Flip flop
FlipFlopschematic_path_pres
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Selectorschematic_path_pres
Circuit Description: DecisionSelective Feedback
DSF_sel
ECL Selector
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Circuit Description: DecisionSelective Feedback
Design of critical path using sum of OCTC
HBTcascode
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Circuit Description: DecisionSelective Feedback
Design of critical path using sum of OCTC
1.Minimize transistor time constants, bybiasing at peak ft / fmax collector currentdensity
HBTcascode
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Circuit Description: DecisionSelective Feedback
Design of critical path using sum of OCTC
1.Minimize transistor time constants, bybiasing at peak ft / fmax collector currentdensity
2.Minimize the interconnect capacitance to tailcurrent ratio through layout and byincreasing collector current
HBTcascode
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Circuit Description: DecisionSelective Feedback
Design of critical path using sum of OCTC
1.Minimize transistor time constants, bybiasing at peak ft / fmax collector currentdensity
2.Minimize the interconnect capacitance to tailcurrent ratio through layout and byincreasing collector current
3.Minimize voltage swing (or load resistor)
HBTcascode
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dfe_publish
DIE Photo
1.Broadband frontend
2.Slicers
3.Decisionselectivefeedback
4.Output driver
5.Clock Buffer
1
2
3
5
4
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Measurements: BERT20-ft SMA cable
■20-ft SMA cable
►dB of attenuation at5GHz
■Measurement Goal:Highest frequency BERTtest possible at theUniversity of Toronto
20-ft SMA cable S21
20ft_sma_cable
smacable
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2to31_input
Measurements: BERT10-Gbps 20-ft SMA cable
2to31_equalized_error_free_
Input Eye – 20-ft SMA Cable
Equalized Output Eye
Jitterpp = 10.22ps; SNR = 13.13
Rise time = 18.7ps; Vpp = 290mV
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Measurements: 40-Gbps LargeSignal Measurements
40GH_LargeSignalSetup_pres
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Measurements: 40-Gbps LargeSignal Measurements
■9-ft SMA cable
►dB of attenuation at20GHz
■Measurement Goal:Prove error freefunctionality at 40-Gbps
9-ft SMA cable S21
smacable
sparam_9ft_cable
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Measurements: 40-Gbps LargeSignal Measurements
39p5G
39p5g_1_3
Input Eye – 9-ft SMA Cable
Equalized Output Eye
Jitterpp = 5.11ps; SNR = 9.1
Rise time = 13.67ps; Vpp = 320mV
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Measurements: 40-Gbps LargeSignal Measurements
■Manually verified508-bit sequence(4x27-1 PRBS) viathe waveformcapture feature ofoscilloscope
■Errors in middlewaveformindicated byarrows
Reference
DFE output
  = 0
DFE output
  ≠ 0
39p5G_2to7_sequence2
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Measurement Summary
Technology
Jazz Semiconductor0.18 m SiGe BiCMOS
Supply Voltage
3.3V
Data Rate
40-Gbps
Power Dissipation
760mW
      Broadband front end
95mW
      Slicers
160mW
      Decision Selective Feedback
225mW
      Output Driver
95mW
      Clock Path
185mW
Return Loss
< -10 dB up to 40 GHz
Output Peak-to-Peak Jitter
5.11ps @ 40 Gbps
Rise/Fall time
13.67/6 ps @ 40 Gbps
Output Swing
324mV @ 40 Gbps
Chip Size
1.5mm2
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Conclusion
■Design
►1-Tap look-ahead architecture
►Broadband up to 40-Gbps
►Broadband, linear, low noise input stage
■Performance
►Demonstrated equalization of a 20-ft SMA cable at 10Gbps
●BER of less than 10-12
►At 40-Gbps, the DFE equalized a 9-ft SMA cable witherror free operation
■This is the first 40-Gbps DFE in silicon
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Acknowledgements
■NIT, OIT, CFI for test equipment
■NSERC, Gennum and Micronet for financialsupport
■Jazz Semiconductor for technology access
■CAD tools by the CanadianMicroelectronicsCorportation (CMC)
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Questions?
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Backup
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Fabrication
■Break out circuit of thebroadband front end
■Linear measurements
BreakOut_Photo
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Measurements: S-Parameter
sparameter_Break_notitle
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Return Loss on High Frequency Ports
Broadband Front End S21
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Measurements: BroadbandCharacterization
p1db
1db_compression
1db_compression_vs_freq
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Measurements: BroadbandCharacterization
ALPHAsweep_nosimulation
Offsetschematic_presentatio
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Measurements: BERT
BERTSetup
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Measurements: 40-Gbps LargeSignal Measurements
40GH_LargeSignalSetup