Discrete GateSizingCENG 5270 – Tutorial 9
WILLIAM CHOW
Discrete Gate Sizing
 Given design D that contains:
◦Set of standard cells C
◦Set of pins P on these cells
◦Set of Nets N
D
N1
N2
N3
N4
N5
N6
N7
N8
PI
PO
C1
C2
C3
C4
C5
Sc1
Power = 2uW
Power = 4uW
Power = 8uW
Discrete Gate Sizing
For each standard cell 𝑐∈𝐶, contains: Set of cell types Sc For each of cell type 𝑠∈𝑆, Power(s) denotes the leakage power of cell type s
D
N1
N2
N3
N4
N5
N6
N7
N8
PI
PO
C1
C2
C3
C4
C5
Sc1
Power = 2uW
Power = 4uW
Power = 8uW
Discrete Gate Sizing
For each pin p∈𝑃, Slack(p) denotes timing slack at pin p
D
N1
N2
N3
N4
N5
N6
N7
N8
PI
PO
C1
C2
C3
C4
C5
Sc1
Power = 2uW
Power = 4uW
Power = 8uW
Slack
 Signal at primary input (PI) must arrive primary output (PO) withintarget delay
 Slack = actual arrival time (AAT) – required arrival time (RAT)
10
8
9
9
4
9
6
0
0
10
8
28
23
37
29
19
10
8
9
9
4
9
6
-7
-5
3
3
21
24
30
30
12
Actual arrival time
Required arrival time
Slack
10
8
9
9
4
9
6
0
0
10
8
28
23
37
29
19
10
8
9
9
4
9
6
-7
-5
3
3
21
24
30
30
12
Actual arrival time
Required arrival time
10
8
9
9
4
9
6
-7
-5
-7
-5
-7
+1
-7
+1
-7
Slack
 Total Negative Slack (TNS) denote the absolute value of the totalnegative slack of all PO
TNS = 7
Delay Tables (DT)Slew Tables (ST)
◦Cell delays and slews are defined using delay tables and slew tables.
◦The timing arcs are defined from input pins of the cell to the output pin(rising and falling).
◦Timing arc delay = DT[in_slew, out_load]
◦Timing arc slew = ST[in_slew, out_load]
out_load=50fF
in_slew=80ps
0
20
40
80
160
10
12.5
15.7
18.9
22.0
25.2
20
24.1
30.5
36.7
41.5
50.0
40
30.8
52.4
70.1
82.3
98.2
60
44.7
63.0
99.7
101.5
123.4
80
89.5
91.5
110.5
168.8
210.7
0
20
40
80
160
10
12.5
15.7
18.9
22.0
25.2
20
24.1
30.5
36.7
41.5
50.0
40
30.8
52.4
70.1
82.3
98.2
60
44.7
63.0
99.7
101.5
123.4
80
89.5
91.5
110.5
168.8
210.7
0
20
40
80
160
10
12.5
15.7
18.9
22.0
25.2
20
24.1
30.5
36.7
41.5
50.0
40
30.8
52.4
70.1
82.3
98.2
60
44.7
63.0
99.7
101.5
123.4
80
89.5
91.5
110.5
168.8
210.7
0
20
40
80
160
10
12.5
15.7
18.9
22.0
25.2
20
24.1
30.5
36.7
41.5
50.0
40
30.8
52.4
70.1
82.3
98.2
60
44.7
63.0
99.7
101.5
123.4
80
89.5
91.5
110.5
168.8
210.7
DTfall
STfall
DTrise
STrise
Difficulties
 Changing cell size affect neighboring gates’ delay
10
8
9
6
4
6
6
0
0
10
8
25
23
31
29
19
13
10
8
5
4
6
6
0
0
13
10
26
25
32
31
21
Capacitanceincrease
Slew
decrease
Difficulties
 Other constraints:
◦Capacitance constraint
◦Slew constraint
◦Wire delay
◦Area constraint
◦We don’t consider these in this tutorial
Problem Formulation
Given a design D with timing constraints, determine the cell type 𝑠∈ 𝑆 𝑐 for each cell 𝑐∈𝐶 such that the following objective function is minimized: 𝛼 𝑐∈𝐶 𝑝𝑜𝑤𝑒𝑟 𝑐 +𝑇𝑁𝑆
Problem Formulation
Objective function: 𝛼 𝑝𝑜𝑤𝑒𝑟+ 𝑝𝑜 max 0, 𝑎 𝑝𝑜 − 𝑟 𝑝𝑜 We define the dummy variables 𝑚 𝑝𝑜 as negative margin to replace the max function 0≤ 𝑚 𝑝𝑜 𝑎 𝑝𝑜 − 𝑟 𝑝𝑜 ≤ 𝑚 𝑝𝑜 𝑎 𝑢 + 𝑑 𝑢→𝑣 ≤ 𝑎 𝑣
𝑎 𝑢
𝑑 𝑢→𝑣
𝑎 𝑣
Problem Formulation
Minimize: 𝛼 𝑝𝑜𝑤𝑒𝑟+ 𝑝𝑜 𝑚 𝑝𝑜 Constraints: 0≤ 𝑚 𝑝𝑜 𝑎 𝑝𝑜 − 𝑟 𝑝𝑜 ≤ 𝑚 𝑝𝑜 𝑎 𝑢 + 𝑑 𝑢→𝑣 ≤ 𝑎 𝑣 Constraints are extremely difficult to model!
− 𝑚 𝑝𝑜 ≤0 𝑎 𝑝𝑜 − 𝑟 𝑝𝑜 − 𝑚 𝑝𝑜 ≤0 𝑎 𝑢 + 𝑑 𝑢→𝑣 − 𝑎 𝑣 ≤0
Lagrangian Relaxation
 We integrate the constraints to the original objective function andobtain the Lagrangian-Relaxed Subproblem (LRS):
If we set 𝜇 𝑝𝑜 ′ + 𝜇 𝑝𝑜 =1:
Lagrangian Relaxation
 Based on Kuhn-Tucker conditions, the sum of multipliers on incomingarcs of a node must be equal to the sum of multipliers on its outgoingarcs.
𝑎 𝑠 1
𝑎 𝑠 2
𝑎 𝑣
𝑎 𝑢
𝑎 𝑡 1
𝑎 𝑡 2
𝜇 𝑢→𝑣
𝜇 𝑠 1 → 𝑡 1
𝜇 𝑠 2 → 𝑡 2
𝜇 𝑢→𝑣 = 𝜇 𝑠 1 → 𝑡 1 + 𝜇 𝑠 2 → 𝑡 2 𝑎 𝑣 = 𝑎 𝑠 1 = 𝑎 𝑠 2
Lagrangian Relaxation
We want to use the slack values computed by signoff timer directly. We define: 𝑚 𝑣 = 𝑎 𝑣 − 𝑟 𝑣 𝑚 𝑢→𝑣 = 𝑎 𝑢 + 𝑑 𝑢→𝑣 − 𝑟 𝑣
Graph Model
 Use a graph model that captures the Lagrangian relaxed subproblem
 Select cell size with the graph model
Graph Model
 What is the minimal cost selection?
2
5
1
4
1
2
3
6
1
8
Graph Model
 What is the minimal cost selection?
2
5
1
4
1
2
3
6
1
8
11
Graph Model
 What is the minimal cost selection?
2
5
1
4
1
2
3
6
1
8
1
2
8
6
2
3
7
9
4
2
5
3
3
3
5
4
Graph Model
 What is the minimal cost selection?
2
5
1
4
1
2
3
6
1
8
1
2
8
6
2
3
7
9
4
2
5
3
3
3
5
4
25
Graph Model
◦Begin with an arbitrary size selection
◦Define reference cell types as the current selected cell types
◦For node weight, we consider:
◦Leakage power of cell type
◦Gate delay change without changing downstream cell types
◦For edge weight, we consider:
◦Gate delay change due to change of downstream cell types
Graph Model
Reference delay of timing arc k of cell i with type j: 𝑑𝑒𝑙𝑎𝑦𝑟𝑒 𝑓 𝑘 𝑠 𝑖 𝑗 =𝑑𝑒𝑙𝑎 𝑦 𝑘 𝑡∈𝑓𝑎𝑛𝑜𝑢𝑡 𝑖 𝑐𝑎𝑝 𝑠 𝑡 𝑟𝑒𝑓 Approximate delay under change of fanout cells: 𝑑𝑒𝑙𝑎 𝑦 𝑘 𝑠 𝑖 𝑗 =𝑑𝑒𝑙𝑎𝑦𝑟𝑒 𝑓 𝑘 𝑠 𝑖 𝑗 +Δ𝑐𝑎𝑝 𝑚 ⋅ 𝜕 𝑇 𝑘 𝜕𝑐𝑎𝑝 ​ 𝑟𝑒𝑓 Weight of a subnode 𝑠 𝑖 𝑗 : 𝑤𝑒𝑖𝑔ℎ𝑡 𝑠 𝑖 𝑗 =𝑝𝑜𝑤𝑒𝑟 𝑠 𝑖 𝑗 + 𝑘∈𝑎𝑟𝑐𝑠 𝑠 𝑖 𝑗 𝜇 𝑘 𝑑𝑒𝑙𝑎𝑦𝑟𝑒 𝑓 𝑘 𝑠 𝑖 𝑗 Weight of an edge from 𝑠 𝑖 𝑗 to 𝑠 𝑚 𝑛 : 𝑤𝑒𝑖𝑔ℎ𝑡 𝑠 𝑖 𝑗 → 𝑠 𝑚 𝑛 =Δ𝑐𝑎𝑝 𝑠 𝑚 𝑛 ⋅ 𝑘∈𝑎𝑟𝑐𝑠 𝑠 𝑖 𝑗 𝜇 𝑘 𝜕 𝑇 𝑘 𝜕𝑐𝑎𝑝 ​ 𝑟𝑒𝑓
Graph Model
The Algorithm
 Produce an initial arbitrary solution
 Run static timing analysis
 While objective function is not converge
◦Update Lagrange multipliers
◦Choose size with dynamic programming using the graph model
◦Run static timing analysis
◦Update objective function
Refrences
 [1] M. M. Ozdal, S. Burns, J. Hu, "Gate Sizing and Device Technology Selection Algorithmsfor High-Performance Industrial Designs", ICCAD 2010