CLBs, Slices, and LUTs
Some key features of the CLB architecture include:
• Real 6-input look-up tables (LUTs)
• Memory capability within the LUT
• Register and shift register functionality
Clock Management
Some of the key highlights of the clock management architecture include:
• High-speed buffers and routing for low-skew clock distribution
• Frequency synthesis and phase shifting
• Low-jitter clock generation and jitter filtering
Each 7 series FPGA has up to 24 clock management tiles (CMTs), each consisting ofone mixed-mode clock manager
(MMCM) and one phase-locked loop (PLL)