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Memristive ComputingMemristive Computing
Winter 2013
EE222-lecture7
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OutlinesOutlines
•Background: Memristive Computing
–Definitions
–Technical Area and Research Opportunities
–Memristors and Memristive Devices
•Past and Current Trends
–Memristive Storage Systems
–Memristive Logic and Computing Systems
•Looking into Future
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‘Memristive Computing’‘Memristive Computing’
•What is ‘Memristive Computing’?
–Any set of circuits which utilizes ‘memristive’ electronic propertiesin computing/processing information.
•May or may not include actual ‘memristor’ or ‘memristivedevice’.
–Which behaviors are ‘Memristive’?
•Utilizations of ‘dynamic nonvolatile resistance’ as thefundamental state variable for data storage/computing/etc.
–Alternate term is ‘Resistive Computing’.
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‘Memristive Computing’‘Memristive Computing’
•Focal Areas of Related Research
–Resistive memory system that stores information in its ‘resistance’
•Resistive Random Access Memory (RRAM), Phase-Change RAM(PCRAM), Magnetic RAM (MRAM), etc.
•Nonvolatile-VLSI/SRAM/analog/etc.
–Stateful logic: computes/registers Boolean functions/states
•Stateful NAND, AND, NOR, OR, XOR, XNOR, etc.
•Memristive logic array, pattern matcher/searcher
–Reconfigurable electronics
•Memristors-based threshold logic, memristive FPGA,programmable stateful logic array, adaptable electronics, etc.
–Learning/interconnecting machine that utilizes memristance
•Memristive synaptic network, neuromorphic computing, etc.
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Memristors and Memristive DevicesMemristors and Memristive Devices
•Distinctive Capabilities of Memristors
–Defines the missing link btwn. charge (q) andflux-linkage ()
–Capabilities both for “Resistor” and “Memory”
–“Conditional” SET or RESET, depending onthe applied voltage
•Enables “logic” functions in the memristordevices
•Potential Applications of Memristive Devices
–Analog/binary/multi-level nonvolatile memory
–Analog/digital signal processing
–Reconfigurable systems
–Logic elements
“Conditional” SET and RESET
Memristor as 4th fundamental device
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Memristive Devices and SystemsMemristive Devices and Systems
•Examples
–Hodgkin-Huxley Equation, Flourescent Lamp, Thermistor, etc.
–Memristor is a special case of memristive systems
Current-controlledmemristor
Voltage-controlledmemductor
•Defined by L. Chua & S.M. Kang in 1976
–A class of nonlinear devices whose resistance is controlled by statevariables that incorporate memory effects
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Nanoscale Memristive DevicesNanoscale Memristive Devices
•Nanotechnology Enabled Memristive Devices
–Typically formed in nano crossbar structures
•Capable of ultra dense integration
–Compatible with CMOS process
•Enables hybrid CMOS/Nanodevices integration
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Low-Level Nanowire Crossbar StructureLow-Level Nanowire Crossbar Structure
•NanoelectronicsDevices
–At each cross point of ananowire crossbar
•CMOS-nano Interface
–PINs on top of CMOSStack
•Technical Issues
–Addressability ofnanodevices
–Alignment of CMOS PINarray & nanowirecrossbar
NanowiresNanowires
NanodevicesNanodevices
NanowiresNanowires
Interface PINsInterface PINs
Top level wiresTop level wires
of CMOS stackof CMOS stack
oxideoxide
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CMOS/Nano Hybrid IntegrationCMOS/Nano Hybrid Integration
•Hybrid 2D/3D Integration
–Reconfigurable Nano+CMOS
–Extendable to multi-layeraddressing/interconnection
•Ultra-dense MemristiveNanoelectronics
–2D/3D analog/digital memory
–Large-scale logic array
–Neuromorphic chips
–Memristive signal processing
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Memristor-Embedded CMOSMemristor-Embedded CMOS
Grand challenge:
How can we avoid the complex hybrid technology for CMOS/Nano co-integration?
active
M3
M4
M1
M2
Nano layer
Nanowire crosspoint devices
CMOS layer
active
InterlayerPINs array
Memristive-via devices
FPNI structure
CMOL structure
UCSC’s Memristor-embedded CMOS
M3
M4
M1
M2
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OutlinesOutlines
•Background: Memristive Computing
–Definitions
–Technical Area and Research Opportunities
–Memristors and Memristive Devices
•Past and Current Trends
–Memristive Storage Systems
–Memristive Logic and Computing Systems
•Looking into Future
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Memristive Storage SystemsMemristive Storage Systems
•Ultra-Dense Persistent Memory
–Compatible to hybrid integration with CMOS
–Variability-immune storage capability
–Fast read/write access
–Low-power addressability and readability
•Search Capability within Memory Systems
–Ultra-dense nonvolatile storage for data-intensive applications
–Low-latency search for data/text/image/etc.
–Energy-efficient storage/search operation
–E.g., Content Addressable Memory (CAM) Systems, pattern matchers,etc.
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Memristive Device as Persistent MemoryMemristive Device as Persistent Memory
•Key factors of importance
–Physical Geometry
–Process/Thermal Reliability
–Embedding Compatibility into CMOS
–3D Stackability
•Challenges for Device Technology
–Number of Storage Bits/Device
–Retention >10 years
–Endurance > 1017
–Read/Write Energy < 1fJ/bit
–Read/Write Speed < 1ns
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RRAM Device ModelsRRAM Device Models
•Functional Model
–Captures the threshold sensitive bistableresistance state
–Neglecting timing related performance
•Valid for functional circuit simulations
•Behavioral Model
–With added behaviors of switching transients
•Valid for behavioral circuit simulations
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RRAM Device ModelsRRAM Device Models
•Statistical Model
–Captures the variability of device parameters
–Thresholds, resistance state, and switching speed with statisticaldistribution
•Valid for statistical estimation of circuit reliability
Behavioral model
Statistical model
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Classes of Nonvolatile RAMClasses of Nonvolatile RAM
•Classes of NVRAM
–Charge-based memory: EEPROM, FLASH, SRAM
–Memristive (resistive) memory: PCRAM, MRAM, RRAM
•Technology Issues with RRAM
–Unreliable device performance (Variability)
–Multi-layer memory integration
•Circuit issues
–Speed & Power consumption for read/write operations
–Performance degradation by “Sneak currents”
–“Data-pattern” sensitive power & read/write performance
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Issues on Passive Array of RRAMsIssues on Passive Array of RRAMs
•Technology issues
–Unreliable device process (Variability)
–Multi-layer memory integration
•Circuit issues
–Power consumption for Write/Read operations
–Performance degradation by “Sneak currents”
–“Data-pattern” sensitive power & read performance
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How to deal with “Sneak Currents”?How to deal with “Sneak Currents”?
With selection devices
(e.g., 1T1R or 1D1R)
Trading-off with power
( 0 ≤ vX < vR )
Forced bit-line voltages
(e.g., TIA type)
Performance
(a)
(b)
(c)
Sensing margin
Large
Narrow
Large
Speed
Fast
Fast
Slow
Power
Low
Moderate ~ High
Low
2D capacity
Low
High
High
3D stackability
Challenging
Good
Good
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Sensing Behaviors of RRAMsSensing Behaviors of RRAMs
•Passive RRAM with Resistive Terminations
–Sensing performance is highly dependent on the stored “Data-pattern”, due to “Sneak Currents”
–The more low-resistance cells lead to the lower sensing margin
Data-pattern sensitive Readperformance (128x128 array)
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RRAM ModelingRRAM Modeling
•Analysis and Estimation of RRAM Performance (m×n array)
–Full node analysis needs to solve for
–Computation efficient statisticalmodel for analysis of data- andvariability-dependency
–Sub-grouping for modeling
•GI : cell to be read (k, l)
•GII : cells in reading row
•GIII : cells in reading column
•GIV : all the others
for j=1, 2, …, m
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2x2 Equivalent Memory Model2x2 Equivalent Memory Model
•2×2 equivalent model forn×m RRAM array
–Each group is represented ina single equivalent admittance
–Capable of flexible analysisand ease of simulation
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2x2 Model Results2x2 Model Results
•Example for 128×128 array
–Conditions : =ROFF/RON=103, (ROFF=10 M, RON=10 k)
–Note: Data-pattern dependent (=ROFF/RS) is desirable
(a) Detection margin
(b) Average cell current
Symbols : n×m simulation
Lines : 2×2 model
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Array Size DependencyArray Size Dependency
•Optimal RS (RS.opt)
–RS.opt =~RON (small array)
< RON (large array)
–Sensitive to data-pattern
•Detection margin (vS)
–Decreases with array size
–Sensitive to data-pattern
–For 1% margin, n & m <128
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Data-Pattern DependencyData-Pattern Dependency
•Highly sensitive performance to data-pattern
–opt/ is approximately linear to data probability
–Data dependent optimum -ratio (opt=ROFF/RS.opt) is desirable
•-ratio (=ROFF/RON) dependency
–Generally good for larger -ratios (rapidly desensitized as >102)
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Adaptable RS.opt ExampleAdaptable RS.opt Example
•128×128 RRAM array
–RON=10k, ROFF=10M (=103)
–RS constructions by
•Reconnecting a part of unreadRRAM (x=5)
•Dedicated ROFF rows (y=35)
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Performance ComparisonPerformance Comparison
•Worst case vs. self-adaptable design
–Self-adaptable design shows the larger vS and low Icell.av ,simultaneously, compared to the worst-case design
–Especially for low probability cases
Average improvement:
+ 46% for vS increment
+ 14% current reduction
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Complementary Memory CellComplementary Memory Cell
•Complementarily written two devices cell (CR-cell)
–Provides data-dependent equivalent sense resistance (RS.eq )
1R-cell
CR-cell
Readout circuitconfiguration
Sense resistance
Normalizeddetection margin
Normalizedaverage current
>
<
<
>
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Array Properties of CR-cell ArrayArray Properties of CR-cell Array
•Features
–Lower design complexity
•With no optimization process for RS
–Data-dependent equivalent RS
–Reduced effective density
–Doubled number of sneak paths bycomplementary devices
•Data-pattern dependency
–Constant detection margin
•With larger window
–Regulated readout currents
•With smaller values
2x2 array of CR-cell memories
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n xm Dimensional CR-cell Arrayn xm Dimensional CR-cell Array
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Write-Mode ConfigurationWrite-Mode Configuration
•2-Step ‘WORD-wise’ Writing
–Step-1: RESET for all devices of a selected word line
–Step-2: SET for selected bit devices (other devices are halfwayselected)
Step-1: RESET
Step-2: Selective SET
Bit controlled
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Read-Mode ConfigurationRead-Mode Configuration
•‘WORD-wise’ READ
–Comparison VS with VREF
•Reference generation
–Desirable to be data-dependent
–Finding median VS bydedicated ROFF & RON columns
–Each REF cell hascomplementary devices(pIII=0.5)
–Reference buffer isolatescapacitances of SAs
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Variability Effect on Read PerformanceVariability Effect on Read Performance
•For a 128x128 array:
–Resistances: log-N dist. w/i =20%
–RON.0=10k, ROFF.0=10M
–Array size=128x128
–REF sections for every 8-bits
3VS.LRS
Data-dependent VREF
VS.LRS
VS.HRS
3VS.HRS
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Performance Comparison (I)Performance Comparison (I)
•Array size dependency
–Optimally designed 1R-cell array vs. CR-cell array
–CR-cell memory is capable of ~4x larger size
Symbols : CR-cells array
Thin lines: 1R-cells array
1R-cell RRAM
CR-cell RRAM
Data-pattern independentdetection performance
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Performance Comparison (II)Performance Comparison (II)
•Data-pattern Dependency
–Optimally designed 1R-cell array vs. CR-cell array
–Lower current consumption for all cases
–Data-independent detection performance
Symbols : CR-cells array
Thin lines: 1R-cells array
Voltage Detection Window
Sensing Current
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Ternary CAM StructureTernary CAM Structure
•Content Addressable Memory (CAM) Architecture
–RRAM-based CAMs array (unit array size: nxm)
–Capable of storage/search of ternary states
–Returns a matched address
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Ternary CAM CellTernary CAM Cell
•NOR-type Content Match
–Control bits: Word Select (WS), Search/Write Enables (SE, WE)
–Input/Output: Contents Lines (C, C), Match Line (ML)
•Ternary BITs Read/Search
–2-bit complementary storage
–“don’t care” Search with C=C=0
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CAM Performance FactorsCAM Performance Factors
•Maximum Size of Unit CAM Array
–Limited in parts by the Latency & Power specification
•# of SLs: determined by Latency
•# of WLs: determined by power consumption
–There is no “Sneak” effect
•Latency participating Components
–Input part: ‘Contents driving delay’, ‘VX charging time’
–Evaluation part: ‘ML pre-charging time’, ‘ML pull-down time’
–Output part: ‘SA delay’, ‘Decoding time’
•The other delay components will not affect the Latency
•Power Consumption
–Dominated by currents through RRAMs
–Total power consumption: ~proportional to # of WLs
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Reduction of Writing PowerReduction of Writing Power
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OutlinesOutlines
•Background: Memristive Computing
–Definitions
–Technical Area and Research Opportunities
–Memristors and Memristive Devices
•Past and Current Trends
–Memristive Storage Systems
–Memristive Logic and Computing Systems
•Looking into Future
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Computing in Memristive DevicesComputing in Memristive Devices
•Three distinctive functions ofmemristive devices
–Programmable interconnects
–Nonvolatile memory
–Conditional SET and RESET ofmemristance
•Property of Conditional SET or RESET Enables:
–Memristive “logic” and “computing” capable of reconfiguration
–High density logics and signal processing through 3D integration
•e.g., CPU embedded memory
–With capability of nonvolatile memory
•logic functioning + registering
–Extends Moore’s Law beyond the CMOS limit
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Memristive Stateful Logic GateMemristive Stateful Logic Gate
•Stateful NAND Gate via Material Implication
Device-Q can be SET “conditionally”depending on the status of P.
“Stateful” logic, functioning NAND andregistering the output in Q.
Implication condition:
VEVL < VSET
VSET > VCLOSE
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•Reconfigurable logic arrayarchitecture
–2D or 3D structured logic array
–Multiple fan-in/fan-out
•Device technology for reliablelogic functioning
–Distinctive sets of devicecharacteristics regardingaccidental interconnectionchange
•Design Paradigm Shift
–Fine grain pipelined logicarchitecture
Issues for Large Scale Logic ArrayIssues for Large Scale Logic Array
1-D array
2-D array
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Issues: Parallel ExecutionIssues: Parallel Execution
•Pipelined executions to reduce data latency
–Simultaneous executions of
non-overlapped logics
–Overheads: control switches
and load resistors
Example 3-gates logic
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Issues: Simultaneous ImplicationsIssues: Simultaneous Implications
•Reduction of data latency
–Single 2-input NAND execution requires 3-steps of implications
•Initialization (CLEAR) + two implication steps (Conditional SET)
–High fan-ins seriously increase the data latency
–Simultaneous executions of multiple implications are desirable
•k-input NOR gate with simultaneous implications
–Significantly reduces the latency for high fan-ins
Fixed-RG
Scaled RG-EQ 1/(k+1)
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Issues: Duplication (I)Issues: Duplication (I)
•Explicit duplication requirement for fan-out capability
Inversion required for involution!
More steps required for large fan-outs!
If Q turned ON first, then R cannot beturned ON!
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Issues: Duplication (II)Issues: Duplication (II)
•Solution for simultaneous duplication: AND operation
Step-1: SET
Step-2: Simultaneous duplication
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Issues: Mapping to FPNI Fabric (I)Issues: Mapping to FPNI Fabric (I)
•NOR operation
–Executed during odd numbered schedules
–Implication voltages: VCLEAR, VSET, VCOND-
Mode
Step
VI
SI
VII
SO
write
1
0
VCLEAR
0
2
0
0
3
VCOND-
1
VSET
0
4
1
0
read
1
VCLEAR
0
0
2
0
0
3
VSET
0
VCOND-
1
4
0
VCOND+
1
RESET initialization
SET initialization
NOR operation
OR operation & duplication
Next pipelined schedule
Example of 2-input NOR execution:
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Issues: Mapping to FPNI Fabric (II)Issues: Mapping to FPNI Fabric (II)
•OR & duplication
–Executed during even numbered schedules
–Implication voltages: VSET, VCLEAR, VCOND+
–Dedicated switch (SD) for duplication control
Mode
Step
VI
SI
VII
SO
SD
write
1
0
0
0
2
0
VSET
0
0
3
1
0
0
4
VCOND+
1
VCLEAR
0
1
read
1
VCLEAR
0
0
0
2
0
0
0
3
VSET
0
VCOND-
1
0
4
0
VCOND+
1
0
RESET initialization
SET initialization
NOR operation
OR operation & duplication
Next pipelined schedule
Example of 2-input 2-output OR execution:
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Issues: Mapping to FPNI Fabric (III)Issues: Mapping to FPNI Fabric (III)
•2D Stateful NOR Gate and it’s FPNI mapping
2D implementation of k-input NOR gate
Mapping to FPNI fabric
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Issues: Implication VoltagesIssues: Implication Voltages
•Example for k-input NOR gate
–Condition: VCLOSE=-1V, VOPEN=1V, =ROFF/RON=102, =ROFF/RG=2
–Wide enough triangular solution space of (VSET, VCOND-)
Valid voltages space for simultaneous executionsof multiple implications
Simulation results for k=8, =8
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Base Unit for Large-Scale Logic ArrayBase Unit for Large-Scale Logic Array
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Base Unit for Large-Scale Logic ArrayBase Unit for Large-Scale Logic Array
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Capability of Signal ProcessingCapability of Signal Processing
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Design Paradigm Shift (I)Design Paradigm Shift (I)
•Logic Representation
–Staged OR-NOR Graph (SONG)
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Design Paradigm Shift (II)Design Paradigm Shift (II)
•Hierarchical Assembly: Data Synchronization
–Example of 2-bit adder
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Design Paradigm Shift (III)Design Paradigm Shift (III)
•Hierarchical Assembly: Data Synchronization
–Example of hierarchical 4-bit adder
2-bit adder2-bit adder
2-bit adder2-bit adder
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•Logic input (x, y ), and output (p)
–Steps and Control for Logic Implication
–Truth Table for XOR operation
Resistive Multiplication: XORResistive Multiplication: XOR
VP
S1
S2
Mode
Step-I
VRST
1
0
Step-II
VSET
0
1
Mode
0
0
0
0
0
1
0
1
1
0
0
1
1
1
0
0
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Implication Conditions for XORImplication Conditions for XOR
(VEVL, VSET)=
(1, 1.5)xVCLOSE
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Results of XOR OperationResults of XOR Operation
Used Device Parameters:
RON=10k
ROFF=1M
VCLOSE=1V
VOPEN=-1V
Thold=10ns
Circuit Parameters:
VSET=1.5V
VRST=-1.5V
VEVL=1V
TSTEP=20ns
0
0
0
0
1
1
1
0
1
1
1
0
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•Logic input (x, y ), and output (q)
–Steps and Control for Logic Implication
Resistive Multiplication: XNORResistive Multiplication: XNOR
VP
VQ
S1
S2
S3
S4
Mode
Step-I
VRST
VRST
1
0
0
1
Step-II
VSET
-
0
1
0
0
Step-III
VEVL
VSET
0
0
1
1
Step-I
Step-II
Step-III
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
0
0
0
0
0
1
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Results: XNOR operationResults: XNOR operation
Used Device Parameters:
RON=10k
ROFF=1M
VCLOSE=1V
VOPEN=-1V
Thold=10ns
Circuit Parameters:
VSET=1.5V
VRST=-1.5V
VEVL=1V
TSTEP=20ns
0
0
0
1
0
1
1
0
1
0
1
0
1
1
0
1
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Application to Pattern MatcherApplication to Pattern Matcher
![Example for a Vector Multiplication
Input: 𝐗=[ 𝑥 0 , 𝑥 1 , 𝑥 2 ,…, 𝑥 𝐿−1 ]
Ref : 𝐘=[ 𝑦 0 , 𝑦 1 , 𝑦 2 ,…, 𝑦 𝐿−1 ]
Output: 𝑐=𝑘(𝐗∙𝐘)=𝑘 𝑖=0 𝐿−1 𝑥 𝑖 𝑦 𝑖](data/images/img158.png)
Vxy is proportional to the correlation betweenthe input vector X and the reference vector Y.
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Results: XOR-Based Pattern MatchResults: XOR-Based Pattern Match
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Matcher Application to Pattern SearchMatcher Application to Pattern Search
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Pattern Search ResultsPattern Search Results
–Each matcher branch set to store one of the eight binary encodedcharacters of “ACFILNOR”.
–Input character stream of “CALIFORNIA” was fed to the matcher.
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Memristive Computing: Pros & ConsMemristive Computing: Pros & Cons
•Enabling Opportunities
–Low-power nonvolatile computing (zero standby leakage)
–No requirement for dedicated registers (stateful)
–Fast computing capability by parallel processing (deep pipeline)
–Instant resilience at power shutoff
•Barriers to Large-Scale Integration
–Static power consumption (non-zero active current)
–Relatively complex configuration and implication schedule
–Sensitivity to the multiple levels of bias voltages
–Systems’ lifetime (determined by devices’ reliability ‘Endurance’)
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OutlinesOutlines
•Background: Memristive Computing
–Definitions
–Technical Area and Research Opportunities
–Memristors and Memristive Devices
•Past and Current Trends
–Memristive Storage Systems
–Memristive Logic and Computing Systems
–Pros and Cons of Memristive Computing
•Looking into Future
68
Future…Future…
•Memristive Technology EnabledNonvolatile Reconfigurable Systems on a Memristive System
–That can adapt its own system configuration & applicationdynamically to environment & requirement
